rockchip: spl: Fix bootargs append support for kernel boot

Change-Id: I4a0aea5587a70544b66493dc343c9a36a6c4731e
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

rockchip: spl: Add SPL_RESERVE_ATF_MEM support

Change-Id: Ic582f48785d77c748f0f832b42e1751ec6b72a39
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

rockchip: spl: Add weak spl_rk_board_prepare_for_jump()

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3bdc20ff399253e31ee3842312c6fc20dbf31d74

rockchip: spl: Change spl_fdt_fixup_memory to weak func

Support implement spl_fdt_fixup_memory based on board specific needs.

Change-Id: Ib7074d9339387bd251ca0839074e21e13a6d09bf
Signed-off-by: Xuh

rockchip: spl: Change spl_fdt_fixup_memory to weak func

Support implement spl_fdt_fixup_memory based on board specific needs.

Change-Id: Ib7074d9339387bd251ca0839074e21e13a6d09bf
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

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rockchip: Add arch timer 1Ghz support

Change-Id: I8e58b15be1823e732852a2aa76cc98813e6b4fe9
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

rockchip: spl: Add increase size support when fix fdt failed

Change-Id: I0daf1d60671ab4a7e9b78f828bd334fa020e9f31
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

common: spl: Add HW-ID dtb support for thunderboot

Steps to enable HW-ID dtb on thunderboot:
1、configs: Enable the following configurations:
CONFIG_SPL_ROCKCHIP_HWID_DTB
CONFIG

common: spl: Add HW-ID dtb support for thunderboot

Steps to enable HW-ID dtb on thunderboot:
1、configs: Enable the following configurations:
CONFIG_SPL_ROCKCHIP_HWID_DTB
CONFIG_ADC
CONFIG_SPL_ADC_SUPPORT
CONFIG_SARADC_ROCKCHIP_V2 or CONFIG_SARADC_ROCKCHIP
2、dts: add u-boot,dm-spl on saradc node
3、Add HW-ID description for packaging boot.img:
+ #_saradc_ch1_10 {
+ data = /incbin/("/home/nickey/211/3562_dict/sdk/kernel/arch/arm64/boot/dts/rockchip/rk3562-y03-v10.dtb");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x208000>;
+ hash {
+ algo = "sha256";
+ };
+ };
+
kernel {
data = /incbin/("@KERNEL_IMG@");
type = "kernel";
@@ -43,7 +55,7 @@
conf {
description = "Boot Linux kernel with FDT blob";
rollback-index = <0x0>;
- fdt = "fdt";
+ fdt = "#_saradc_ch1_10", "fdt";
kernel = "kernel";
signature {

Tested-On: RK3562
Change-Id: If38f49296f1073e69262da21b5502b1437eb2744
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

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rockchip: spl: Add fixup kernel dtb memory node support

1. This commit is mainly for spl thunderboot.
2. How to fix is based on ddr_mem atags from ddr bin.

Change-Id: I143a2bdfdf077dffc73e8f000c4b5

rockchip: spl: Add fixup kernel dtb memory node support

1. This commit is mainly for spl thunderboot.
2. How to fix is based on ddr_mem atags from ddr bin.

Change-Id: I143a2bdfdf077dffc73e8f000c4b5114b78d3534
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

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rockchip: fpga: Add SPL_FPGA_ROCKCHIP option

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If1e96799e29dde22878aceb23630839dac3e5d27

rockchip: spl: Fix code bug generate from commit c07b486e4fc

Brief commit message:
c07b486e4fc rockchip: spl: Improve handle of boot mode reg info when
deciding next stage

While push this commit, m

rockchip: spl: Fix code bug generate from commit c07b486e4fc

Brief commit message:
c07b486e4fc rockchip: spl: Improve handle of boot mode reg info when
deciding next stage

While push this commit, mistakenly delete break;
behind deciding next_stage is U-Boot from boot mode reg.

Change-Id: I07a9b77f1ba8db22734524225e6a6f9957250403
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

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rockchip: spl: Improve handle of boot mode reg info when deciding next stage

1. For those use os reg which can't reset by NPOR, like rk3588, rk3562.
These os reg have random value after power on by

rockchip: spl: Improve handle of boot mode reg info when deciding next stage

1. For those use os reg which can't reset by NPOR, like rk3588, rk3562.
These os reg have random value after power on by hardware.

2. Now, only specific reg boot mode indicates that next stage is U-Boot.
Otherwise, the next stage should be kernel.

Change-Id: Ib5313261886feb88251e1be294b4c2a0b18ad016
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>

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rockchip: spl: support bootrom boot id for rk3576

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7dbf20342514281864e58fd3fb2ccd32cae0c00

rockchip: spl: Add CONFIG_PCIE_EP_SUPPORT limit for rockchip_pcie_ep_get_firmware()

Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: Ib928b90a3d60d444aad18d4b373a11840b25bcd2

rockchip: spl_tb: Force to enter uboot when ctrl+C is pressed

On the other hand, Perfect the function of spl_next_stage() and
Keep PC hotkey/VolumeUp key the highest priority.

Signed-off-by: Xuhui

rockchip: spl_tb: Force to enter uboot when ctrl+C is pressed

On the other hand, Perfect the function of spl_next_stage() and
Keep PC hotkey/VolumeUp key the highest priority.

Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: I5046ea926097e817ac959b5561a40b4bb7bff5f8

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rockchip: spl: Add hotkey support & Fix brom_download()

Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: I223485db626a0bb1150e46c822c38d3099f35999

rockchip: spl: Fix fwver prefix

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I81bf2c18b52a20bb4a881882f1d0a3a2b5da555a

rockchip: board: Add "fwver" into bootargs

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9faefaa2dbef83adc07e0e0e4968d41b93833ed0

rockchip: spl: Add ctrl+b to enter brom download

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia75143b44e35fbe4b828eeef95c8848b94ee2292

rockchip: pcie-ep-boot: Add pcie ep boot function

This is test on rk3588 evb4/evb4v20.
Steps:
1. Init PCIe EP with:
BAR0: 32bit nonprefetchable, control area, at 0x3c000000
BAR2: 64bit prefetchable,

rockchip: pcie-ep-boot: Add pcie ep boot function

This is test on rk3588 evb4/evb4v20.
Steps:
1. Init PCIe EP with:
BAR0: 32bit nonprefetchable, control area, at 0x3c000000
BAR2: 64bit prefetchable, data area, at CONFIG_SPL_LOAD_FIT_ADDRESS
BAR4: EP wired register

2. Waiting for Linkup;
3. Wating for firmware and RUN command;
4. boot with RAM partition.

Test with RC function driver pcie-rkep.c in host side.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I91e8a3e4159668d57c806663ad4faab93585e6d7

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rockchip: spl: Handle unexpected boot mode for thunder boot

On some platform, the default value of CONFIG_ROCKCHIP_BOOT_MODE_REG
is unknown when code boot.

Signed-off-by: Joseph Chen <chenjh@rock-c

rockchip: spl: Handle unexpected boot mode for thunder boot

On some platform, the default value of CONFIG_ROCKCHIP_BOOT_MODE_REG
is unknown when code boot.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I60f2ab9815e06defd865cdcca7d3e7f1d47fe76b

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rockchip: spl: Add arch_fpga_init() call

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ibe76088f174cbc28a355195a5e80fac239eeb827

rockchip: add and enable pstore for uboot log

Uboot print log to linux pstore buffer, which
can be read by linux.

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I35b5f988ef163f3

rockchip: add and enable pstore for uboot log

Uboot print log to linux pstore buffer, which
can be read by linux.

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I35b5f988ef163f3d1f33f992e05da09180f2baa7

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rockchip: spl: change the secure otp macro as CONFIG_SPL_ROCKCHIP_SECURE_OTP

Since the driver is split in deferent platforms.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie5793fe

rockchip: spl: change the secure otp macro as CONFIG_SPL_ROCKCHIP_SECURE_OTP

Since the driver is split in deferent platforms.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie5793fe83093557a245b0f3fcbfce835d8cef8b8

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rockchip: spl: init gd->flags as dummy

This "dummy" is initialized by board_init_f_boot_flags()
since commit:
(034db99592 dm: serial: support always use uart debug mode)

Signed-off-by: Joseph Chen

rockchip: spl: init gd->flags as dummy

This "dummy" is initialized by board_init_f_boot_flags()
since commit:
(034db99592 dm: serial: support always use uart debug mode)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6afd1133fb95fbf7aa9366dbeb70625f8ab8771d

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rockchip: spl: support low power detect

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ibcb5996369348d31248596dcdb5018ad6526786e