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/rk3399_rockchip-uboot/board/keymile/kmp204x/
H A Dpbi.cfg12 091380c0 000009C4
14 091380c0 000009C4
16 091380c0 000009C4
19 091380c0 000009C4
21 091380c0 000009C4
23 091380c0 000009C4
25 091380c0 000009C4
27 091380c0 000009C4
29 091380c0 000009C4
31 091380c0 000009C4
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darm32_macros.S9 mrc p15, 0, \reg, c0, c0, 0
13 mrc p15, 0, \reg, c0, c0, 1
17 mrc p15, 0, \reg, c0, c0, 5
21 mrc p15, 0, \reg, c1, c0, 0
25 mcr p15, 0, \reg, c1, c0, 0
29 mcr p15, 0, \reg, c1, c0, 1
33 mrc p15, 0, \reg, c1, c0, 1
37 mcr p15, 0, \reg, c1, c0, 2
41 mrc p15, 0, \reg, c1, c0, 2
61 mcr p15, 0, \reg, c2, c0, 0
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A Dlowlevel_init_ca15.S14 mrc p15, 0, r4, c0, c0, 5 /* mpidr */
47 mrceq p15, 0, r0, c1, c0, 1 /* actlr */
49 mcreq p15, 0, r0, c1, c0, 1
52 mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
58 mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
66 mcrne p15, 1, r0, c9, c0, 2
72 mrc p15, 0, r0, c1, c0, 1
74 mcr p15, 0, r0, c1, c0, 1
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dstart.S49 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
68 mrc p15, 0, r0, c1, c0, 1
70 mcr p15, 0, r0, c1, c0, 1
79 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
81 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
85 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
164 mrc p15, 0, r0, c1, c0, 0
176 mcr p15, 0, r0, c1, c0, 0
179 mrc p15, 0, r0, c1, c0, 0 @ read system control register
181 mcr p15, 0, r0, c1, c0, 0 @ write system control register
[all …]
H A Dcache_v7_asm.S29 mrc p15, 1, r0, c0, c0, 1 @ read clidr
41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
43 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
74 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
103 mrc p15, 1, r0, c0, c0, 1 @ read clidr
114 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
116 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
H A Dnonsec_virt.S33 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
49 mcr p15, 0, r5, c12, c0, 1
62 mrc p15, 0, r5, c1, c0, 1
64 mcr p15, 0, r5, c1, c0, 1
69 mrc p15, 0, r5, c1, c0, 1
71 mcr p15, 0, r5, c1, c0, 1
92 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
117 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
192 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
196 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
[all …]
H A Dpsci.S183 mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
207 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
235 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
243 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
245 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
253 mrc p15, 0, r0, c1, c0, 1 @ ACTLR
255 mcr p15, 0, r0, c1, c0, 1 @ ACTLR
268 mrc p15, 0, r0, c1, c0, 0 @ SCTLR
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S20 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
22 mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
24 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
34 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
36 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
38 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
26 mcr p15, 0, r0, c1, c0, 0
43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
45 mcr p15, 0, r0, c1, c0, 0
54 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
57 mcr p15, 0, r0, c2, c0, 2
60 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
66 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
75 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
77 mcr p15, 0, r0, c1, c0, 0
H A Dpsci_smp.S15 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
18 mcr p15, 0, r1, c1, c0, 0
27 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
/rk3399_rockchip-uboot/board/freescale/t104xrdb/
H A Dt104x_pbi_sb.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
38 091380c0 000FFFFF
H A Dt104x_pbi.cfg10 091380c0 000f0000
15 091380c0 00000100
36 091380c0 000FFFFF
/rk3399_rockchip-uboot/arch/arm/cpu/pxa/
H A Dstart.S108 mrc p15, 0, r0, c1, c0, 0
112 mcr p15, 0, r0, c1, c0, 0
125 mrc p15, 0, \reg, c2, c0, 0
132 mcr p15, 0, r0, c3, c0, 0
136 mcr p15, 0, r0, c2, c0, 0
139 mrc p15, 0, r0, c1, c0, 0
144 mcr p15, 0, r0, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dstih410-clock.dtsi88 clk_ext2f_a9: clockgen-c0@13 {
123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
130 clock-output-names = "clk-s-c0-fs0-ch0",
131 "clk-s-c0-fs0-ch1",
132 "clk-s-c0-fs0-ch2",
133 "clk-s-c0-fs0-ch3";
134 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
141 clk_s_c0_pll0: clk-s-c0-pll0 {
147 clock-output-names = "clk-s-c0-pll0-odf-0";
148 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
[all …]
H A Dstih407-clock.dtsi86 clk_ext2f_a9: clockgen-c0@13 {
118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
125 clock-output-names = "clk-s-c0-fs0-ch0",
126 "clk-s-c0-fs0-ch1",
127 "clk-s-c0-fs0-ch2",
128 "clk-s-c0-fs0-ch3";
135 clk_s_c0_pll0: clk-s-c0-pll0 {
141 clock-output-names = "clk-s-c0-pll0-odf-0";
144 clk_s_c0_pll1: clk-s-c0-pll1 {
150 clock-output-names = "clk-s-c0-pll1-odf-0";
[all …]
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A Dt4_pbi.cfg5 091380c0 00000100
21 091380c0 00100000
/rk3399_rockchip-uboot/arch/arm/mach-zynq/
H A Dlowlevel_init.S14 mrc p15, 0, r1, c1, c0, 2
17 mcr p15, 0, r1, c1, c0, 2
/rk3399_rockchip-uboot/board/freescale/t1040qds/
H A Dt1040_pbi.cfg5 091380c0 00000100
27 091380c0 00000000
/rk3399_rockchip-uboot/board/freescale/t102xrdb/
H A Dt1024_pbi.cfg5 091380c0 00000100
26 091380c0 000FFFFF
/rk3399_rockchip-uboot/board/freescale/t4rdb/
H A Dt4_pbi.cfg11 091380c0 00000100
27 091380c0 00100000
/rk3399_rockchip-uboot/board/freescale/t102xqds/
H A Dt1024_pbi.cfg5 091380c0 00000100
26 091380c0 000FFFFF
/rk3399_rockchip-uboot/cmd/ddr_tool/
H A Dddr_tool_mp.S43 mrc p15, 0, r0, c1, c0, 0 /* CP15 C1 System Control Register */
45 mcr p15, 0, r0, c1, c0, 0 /* for remap VBAR */
47 mcr p15, 0, r0, c12, c0, 0
65 mrc p15, 0, r0, c0, c0, 5
/rk3399_rockchip-uboot/board/freescale/b4860qds/
H A Db4_pbi.cfg5 091380c0 00000100
30 091380c0 00000000
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/
H A Dlowlevel_macro.S99 mrc p15, 0, r1, c1, c0, 0
102 mrc p15, 0, r0, c1, c0, 1
104 mcr p15, 0, r0, c1, c0, 1
113 mcr p15, 0, r1, c1, c0, 0
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dstart.S71 mrc p15, 0, r0, c1, c0, 0
73 mcr p15, 0, r0, c1, c0, 0

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