Home
last modified time | relevance | path

Searched refs:USB3 (Results 1 – 21 of 21) sorted by relevance

/rk3399_rockchip-uboot/drivers/usb/cdns3/
H A DKconfig2 tristate "Cadence USB3 Dual-Role Controller"
5 Say Y here if your system has a Cadence USB3 dual-role controller.
11 bool "Cadence USB3 device controller"
22 bool "Cadence USB3 host controller"
32 bool "SPL support for Cadence USB3 device controller"
43 bool "Cadence USB3 host controller"
53 tristate "Cadence USB3 support on TI platforms"
57 platforms that contain Cadence USB3 controller core. E.g.: J721e.
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_a3700.c336 reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); in comphy_usb3_power_up()
344 reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); in comphy_usb3_power_up()
348 reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), in comphy_usb3_power_up()
355 reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), in comphy_usb3_power_up()
360 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); in comphy_usb3_power_up()
363 reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, in comphy_usb3_power_up()
370 reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); in comphy_usb3_power_up()
377 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, in comphy_usb3_power_up()
380 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, in comphy_usb3_power_up()
387 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); in comphy_usb3_power_up()
[all …]
H A Dcomphy_a3700.h72 #define USB3 2 macro
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A DKconfig20 HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
29 card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host
H A Dclock.c432 NONE(USB3),
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A DKconfig2 bool "DesignWare USB3 DRD Core Support"
6 USB controller based on the DesignWare USB3 IP Core.
56 bool "DesignWare USB3 Host Support on UniPhier Platforms"
67 Enable single driver for both USB2 PHY programming and USB3 PHY
/rk3399_rockchip-uboot/board/theobroma-systems/puma_rk3399/
H A DREADME17 * USB3.0 dual role port
18 * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra186/
H A DKconfig16 micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
/rk3399_rockchip-uboot/board/intel/
H A DKconfig18 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
27 peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
/rk3399_rockchip-uboot/drivers/usb/host/
H A DKconfig19 bool "DesignWare USB3 DRD Core Support"
22 USB controller based on the DesignWare USB3 IP Core.
25 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
30 USB controller based on the DesignWare USB3 IP Core.
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c1170 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1202 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1209 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1216 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1223 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1578 if (serdes_type == USB3) { in serdes_pex_usb3_pipe_delay_w_a()
1792 (serdes_num, USB3)); in serdes_power_up_ctrl()
H A Dhigh_speed_env_spec.h173 USB3, enumerator
/rk3399_rockchip-uboot/board/google/
H A DKconfig42 includes a USB SD reader, four USB3 ports, display port and HDMI
/rk3399_rockchip-uboot/board/rockchip/evb_rk3399/
H A DREADME12 * USB: USB3.0 typc-C port *2 with dwc3 controller
/rk3399_rockchip-uboot/drivers/phy/
H A DKconfig116 Enable this to support the Rockchip USB3.0/DP
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-388-clearfog.dts131 * 5-USB3 overcurrent
132 * 6-USB3 power
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dclock.c319 NONE(USB3),
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra114/
H A Dclock.c301 NONE(USB3),
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dclock.c301 NONE(USB3),
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c401 NONE(USB3),
/rk3399_rockchip-uboot/doc/driver-model/
H A Dusb-info.txt139 and newer (EHCI), and super (5Gbps) which is only available with USB3 and