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Searched refs:REG (Results 1 – 25 of 26) sorted by relevance

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/rk3399_rockchip-uboot/board/imx31_phycore/
H A Dlowlevel_init.S10 .macro REG reg, val macro
33 REG IPU_CONF, IPU_CONF_DI_EN
34 REG CCM_CCMR, 0x074B0BF5
38 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
39 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
41 …REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_…
43 REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
45 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
47 REG 0x43FAC26C, 0 /* SDCLK */
48 REG 0x43FAC270, 0 /* CAS */
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Ddavinci_i2c.c35 REG(&(i2c_base->i2c_con)) = 0;\
44 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
47 stat = REG(&(i2c_base->i2c_stat)); in _wait_for_bus()
49 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
53 REG(&(i2c_base->i2c_stat)) = stat; in _wait_for_bus()
57 REG(&(i2c_base->i2c_stat)) = 0xffff; in _wait_for_bus()
67 stat = REG(&(i2c_base->i2c_stat)); in _poll_i2c_irq()
72 REG(&(i2c_base->i2c_stat)) = 0xffff; in _poll_i2c_irq()
79 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) in _flush_rx()
82 REG(&(i2c_base->i2c_drr)); in _flush_rx()
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Drk_gpio.c29 #define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \ argument
30 ((readl(REG_H(REG)) & 0xFFFF) << 16))
31 #define WRITE_REG(REG, VAL) \ argument
33 writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
34 writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
36 #define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK)) argument
37 #define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK)) argument
38 #define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \ argument
39 (READ_REG(REG) & ~(MASK)) | (VAL))
42 #define READ_REG(REG) readl(REG) argument
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dpsc.c130 if (REG(PSC_PDSTAT1) & 0x1f) in dsp_on()
133 REG(PSC_GBLCTL) |= 0x01; in dsp_on()
134 REG(PSC_PDCTL1) |= 0x01; in dsp_on()
135 REG(PSC_PDCTL1) &= ~0x100; in dsp_on()
136 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; in dsp_on()
137 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; in dsp_on()
138 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; in dsp_on()
139 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; in dsp_on()
140 REG(PSC_PTCMD) = 0x02; in dsp_on()
143 if (REG(PSC_EPCPR) & 0x02) in dsp_on()
[all …]
H A Ddm644x.c29 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
32 REG(PINMUX1) |= PINMUX1_UART0; in davinci_enable_uart0()
43 REG(VDD3P3V_PWDN) = 0; in davinci_enable_emac()
46 REG(PINMUX0) |= PINMUX0_EMACEN; in davinci_enable_emac()
56 REG(PINMUX1) |= PINMUX1_I2C; in davinci_enable_i2c()
67 REG(PSC_SILVER_BULLET) = 0; in davinci_errata_workarounds()
80 REG(VBPR) = 0x20; in davinci_errata_workarounds()
H A Ddm355.c18 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
28 REG(PINMUX3) |= (1 << 20) | (1 << 19); in davinci_enable_i2c()
H A Dcpu.c120 div = REG(pllbase + offset); in pll_div()
164 base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); in pll_sysclk_mhz()
H A Dda850_lowlevel.c25 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_combtxphy.h12 #define REG(x) ((x) + COMBTXPHY_BASE) macro
14 #define COMBTXPHY_CON0 REG(0x0000)
34 #define COMBTXPHY_CON1 REG(0x0004)
35 #define COMBTXPHY_CON2 REG(0x0008)
36 #define COMBTXPHY_CON3 REG(0x000c)
37 #define COMBTXPHY_CON4 REG(0x0010)
38 #define COMBTXPHY_CON5 REG(0x0014)
43 #define COMBTXPHY_CON6 REG(0x0018)
46 #define COMBTXPHY_CON7 REG(0x001c)
60 #define COMBTXPHY_CON8 REG(0x0020)
[all …]
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Dlowlevel_init.S9 .macro REG reg, val macro
197 REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
199 REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
203 REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
204 REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
242 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
245 REG 0xB8001010, 0x00000004
246 REG 0xB8001004, 0x006ac73a
247 REG 0xB8001000, 0x92100000
248 REG 0x80000f00, 0x12344321
[all …]
/rk3399_rockchip-uboot/lib/dhry/
H A Ddhry_2.c46 #ifndef REG
47 #define REG macro
121 REG One_Fifty Int_Index;
122 REG One_Fifty Int_Loc;
169 REG One_Thirty Int_Loc;
H A Ddhry_1.c72 #ifndef REG
74 #define REG macro
100 void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
117 REG One_Fifty Int_2_Loc; in dhry()
119 REG char Ch_Index; in dhry()
328 void Proc_1 (REG Rec_Pointer Ptr_Val_Par) in Proc_1()
331 REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; in Proc_1()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dap.h21 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/rk3399_rockchip-uboot/include/
H A Dsym53c8xx.h223 #define REG(r) (r) macro
389 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
392 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
395 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
461 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
464 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dpinmux-common.c96 #define REG(pin) _R(0x3000 + ((pin) * 4)) macro
98 #define MUX_REG(pin) REG(pin)
101 #define PULL_REG(pin) REG(pin)
104 #define TRI_REG(pin) REG(pin)
235 u32 *reg = REG(pin); in pinmux_set_io()
257 u32 *reg = REG(pin); in pinmux_set_lock()
284 u32 *reg = REG(pin); in pinmux_set_od()
309 u32 *reg = REG(pin); in pinmux_set_ioreset()
334 u32 *reg = REG(pin); in pinmux_set_rcv_sel()
359 u32 *reg = REG(pin); in pinmux_set_e_io_hv()
[all …]
H A Dcpu.h32 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
/rk3399_rockchip-uboot/drivers/net/
H A Dmcfmii.c32 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument
33 (REG & 0x1f) << 18))
34 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
35 (REG & 0x1f) << 18) | (VAL & 0xffff))
H A Dmpc8xx_fec.c702 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument
703 (REG & 0x1f) << 18))
705 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
706 (REG & 0x1f) << 18) | \
/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip.h496 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ argument
501 .route_offset = REG, \
506 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ argument
507 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
509 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ argument
510 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
512 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ argument
513 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
/rk3399_rockchip-uboot/board/davinci/da8xxevm/
H A Dda850evm.c463 temp = REG(GPIO_BANK2_REG_SET_ADDR); in rmii_hw_init()
465 REG(GPIO_BANK2_REG_SET_ADDR) = temp; in rmii_hw_init()
468 temp = REG(GPIO_BANK2_REG_DIR_ADDR); in rmii_hw_init()
470 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; in rmii_hw_init()
H A Domapl138_lcdk.c293 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) in dspwake()
304 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; in dspwake()
307 REG(PSC0_MDCTL + (15 * 4)) |= 0x100; in dspwake()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h19 #define REG(addr) (*(volatile unsigned int *)(addr)) macro
591 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da830()
598 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da850()
606 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? in get_async3_src()
/rk3399_rockchip-uboot/drivers/mmc/
H A Ddavinci_mmc.c22 #define get_val(addr) REG(addr)
23 #define set_val(addr, val) REG(addr) = (val)
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h19 #define REG(addr) (*(volatile unsigned int *)(addr)) macro
/rk3399_rockchip-uboot/drivers/pinctrl/
H A Dpinctrl-rockchip.c304 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ argument
309 .route_offset = REG, \
314 #define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ argument
315 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
317 #define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ argument
318 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
320 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ argument
321 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)

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