130 	if (REG(PSC_PDSTAT1) & 0x1f)  in dsp_on()
133 	REG(PSC_GBLCTL) |= 0x01;  in dsp_on()
134 	REG(PSC_PDCTL1) |= 0x01;  in dsp_on()
135 	REG(PSC_PDCTL1) &= ~0x100;  in dsp_on()
136 	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;  in dsp_on()
137 	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;  in dsp_on()
138 	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;  in dsp_on()
139 	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;  in dsp_on()
140 	REG(PSC_PTCMD) = 0x02;  in dsp_on()
143 		if (REG(PSC_EPCPR) & 0x02)  in dsp_on()
147 	REG(PSC_CHP_SHRTSW) = 0x01;  in dsp_on()
148 	REG(PSC_PDCTL1) |= 0x100;  in dsp_on()
149 	REG(PSC_EPCCR) = 0x02;  in dsp_on()
152 		if (!(REG(PSC_PTSTAT) & 0x02))  in dsp_on()
156 	REG(PSC_GBLCTL) &= ~0x1f;  in dsp_on()