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/rk3399_rockchip-uboot/fs/zfs/
H A Dzfs_sha256.c78 SHA256Transform(uint32_t *H, const uint8_t *cp) in SHA256Transform() argument
89 a = H[0]; b = H[1]; c = H[2]; d = H[3]; in SHA256Transform()
90 e = H[4]; f = H[5]; g = H[6]; h = H[7]; in SHA256Transform()
99 H[0] += a; H[1] += b; H[2] += c; H[3] += d; in SHA256Transform()
100 H[4] += e; H[5] += f; H[6] += g; H[7] += h; in SHA256Transform()
107 uint32_t H[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a, in zio_checksum_SHA256() local
114 SHA256Transform(H, (uint8_t *)buf + i); in zio_checksum_SHA256()
126 SHA256Transform(H, pad + i); in zio_checksum_SHA256()
128 zcp->zc_word[0] = cpu_to_zfs64((uint64_t)H[0] << 32 | H[1], in zio_checksum_SHA256()
130 zcp->zc_word[1] = cpu_to_zfs64((uint64_t)H[2] << 32 | H[3], in zio_checksum_SHA256()
[all …]
/rk3399_rockchip-uboot/lib/
H A Dsha256.c88 uint32_t A, B, C, D, E, F, G, H; in sha256_process_one() local
138 H = ctx->state[7]; in sha256_process_one()
140 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process_one()
141 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process_one()
142 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process_one()
143 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process_one()
144 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process_one()
145 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process_one()
146 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process_one()
147 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process_one()
[all …]
H A Dsha512.c162 uint64_t A, B, C, D, E, F, G, H; in sha512_process() local
199 H = ctx->state[7]; in sha512_process()
203 P(A, B, C, D, E, F, G, H, W[i], K[i]); in sha512_process()
205 P(H, A, B, C, D, E, F, G, W[i], K[i]); in sha512_process()
207 P(G, H, A, B, C, D, E, F, W[i], K[i]); in sha512_process()
209 P(F, G, H, A, B, C, D, E, W[i], K[i]); in sha512_process()
211 P(E, F, G, H, A, B, C, D, W[i], K[i]); in sha512_process()
213 P(D, E, F, G, H, A, B, C, W[i], K[i]); in sha512_process()
215 P(C, D, E, F, G, H, A, B, W[i], K[i]); in sha512_process()
217 P(B, C, D, E, F, G, H, A, W[i], K[i]); in sha512_process()
[all …]
/rk3399_rockchip-uboot/tools/rockchip/
H A Dresource_tool.c338 uint32_t A, B, C, D, E, F, G, H; in sha256_process() local
388 H = ctx->state[7]; in sha256_process()
390 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process()
391 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process()
392 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process()
393 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process()
394 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process()
395 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process()
396 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process()
397 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process()
[all …]
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/acpi/
H A Dirqroute.h10 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
11 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
/rk3399_rockchip-uboot/arch/x86/include/asm/fsp/
H A Dfsp_types.h68 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
69 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
/rk3399_rockchip-uboot/doc/SPI/
H A DREADME.ftssp010_spi_test30 10800040: 10800000 0002c1f0 0007409c 00032048 .........@..H ..
40 108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ......
41 108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P..........
/rk3399_rockchip-uboot/
H A Dsnapshot.commit1 $Format:%H %cD$
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A DKconfig363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
371 uses a bit faster timings than DDR3-1333H).
442 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
451 PH1 for pin 1 of port H.
476 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
512 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
519 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
526 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
535 PH1 for pin 1 of port H.
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dstm32mp157-pinctrl.dtsi225 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
226 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
245 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
276 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
312 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
313 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
H A Dhi3798cv200-poplar.dts89 gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
H A Dtegra124-nyan.dtsi58 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
449 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
673 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
H A Dtegra20-tamonten.dtsi480 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
481 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
/rk3399_rockchip-uboot/board/nvidia/p2371-2180/
H A Dpinmux-config-p2371-2180.h39 GPIO_INIT(H, 0, OUT0),
40 GPIO_INIT(H, 1, OUT0),
41 GPIO_INIT(H, 2, IN),
42 GPIO_INIT(H, 3, OUT0),
43 GPIO_INIT(H, 4, OUT0),
44 GPIO_INIT(H, 5, IN),
45 GPIO_INIT(H, 6, IN),
46 GPIO_INIT(H, 7, IN),
/rk3399_rockchip-uboot/board/nvidia/e2220-1170/
H A Dpinmux-config-e2220-1170.h32 GPIO_INIT(H, 0, OUT0),
33 GPIO_INIT(H, 1, OUT0),
34 GPIO_INIT(H, 2, IN),
35 GPIO_INIT(H, 3, OUT0),
36 GPIO_INIT(H, 4, OUT0),
37 GPIO_INIT(H, 5, IN),
38 GPIO_INIT(H, 6, OUT0),
39 GPIO_INIT(H, 7, OUT0),
/rk3399_rockchip-uboot/board/nvidia/p2371-0000/
H A Dpinmux-config-p2371-0000.h31 GPIO_INIT(H, 0, OUT0),
32 GPIO_INIT(H, 2, IN),
33 GPIO_INIT(H, 3, OUT0),
34 GPIO_INIT(H, 4, OUT0),
35 GPIO_INIT(H, 5, IN),
36 GPIO_INIT(H, 6, OUT0),
37 GPIO_INIT(H, 7, OUT0),
/rk3399_rockchip-uboot/board/nvidia/p2571/
H A Dpinmux-config-p2571.h31 GPIO_INIT(H, 0, OUT0),
32 GPIO_INIT(H, 2, IN),
33 GPIO_INIT(H, 3, OUT0),
34 GPIO_INIT(H, 4, OUT0),
35 GPIO_INIT(H, 5, IN),
/rk3399_rockchip-uboot/lib/bzip2/
H A Dbzlib_blocksort.c260 Int32 H, i, j, k, l, r, cc, cc1; in fallbackSort() local
300 H = 1; in fallbackSort()
304 VPrintf1 ( " depth %6d has ", H ); in fallbackSort()
309 k = fmap[i] - H; if (k < 0) k += nblock; in fallbackSort()
351 H *= 2; in fallbackSort()
352 if (H > nblock || nNotDone == 0) break; in fallbackSort()
/rk3399_rockchip-uboot/doc/device-tree-bindings/misc/
H A Dintel-lpc.txt20 - intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
/rk3399_rockchip-uboot/board/nvidia/venice2/
H A Dpinmux-config-venice2.h32 GPIO_INIT(H, 2, IN),
33 GPIO_INIT(H, 4, IN),
34 GPIO_INIT(H, 5, OUT0),
35 GPIO_INIT(H, 6, IN),
36 GPIO_INIT(H, 7, OUT1),
/rk3399_rockchip-uboot/doc/device-tree-bindings/input/
H A Dcros-ec-keyb.txt38 /* F4 G F7 H */
/rk3399_rockchip-uboot/board/freescale/mpc837xerdb/
H A DREADME18 H) 1 32-bit, 3.3 V, Mini-PCI slot
/rk3399_rockchip-uboot/board/nvidia/nyan-big/
H A Dpinmux-config-nyan-big.h32 GPIO_INIT(H, 2, IN),
33 GPIO_INIT(H, 4, IN),
34 GPIO_INIT(H, 6, IN),
35 GPIO_INIT(H, 7, OUT1),
/rk3399_rockchip-uboot/board/nvidia/jetson-tk1/
H A Dpinmux-config-jetson-tk1.h31 GPIO_INIT(H, 2, OUT0),
32 GPIO_INIT(H, 4, IN),
33 GPIO_INIT(H, 7, IN),
/rk3399_rockchip-uboot/drivers/video/
H A DKconfig340 understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
359 understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
369 understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
379 understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
392 function, e.g. PH1 for pin 1 of port H.

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