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Searched refs:GENMASK (Results 1 – 25 of 140) sorted by relevance

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/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Ddenali.h23 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
32 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
54 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
66 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
67 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
71 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
72 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
75 #define RE_2_WE__VALUE GENMASK(5, 0)
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/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/
H A Dmaxim-max96755.h21 #define DEV_ADDR GENMASK(7, 1)
28 #define TX_RATE GENMASK(3, 2)
68 #define LINK_CFG GENMASK(1, 0)
71 #define LINK_MODE GENMASK(5, 4)
75 #define LF_1 GENMASK(6, 4)
76 #define LF_0 GENMASK(2, 0)
85 #define TX_STR_SEL GENMASK(1, 0)
94 #define PATGEN_MODE GENMASK(1, 0)
107 #define PULL_UPDN_SEL GENMASK(7, 6)
109 #define GPIO_TX_ID GENMASK(4, 0)
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H A Dmaxim-max96789.h21 #define DEV_ADDR GENMASK(7, 1)
28 #define TX_RATE GENMASK(3, 2)
68 #define LINK_CFG GENMASK(1, 0)
71 #define LINK_MODE GENMASK(5, 4)
79 #define LF_1 GENMASK(6, 4)
80 #define LF_0 GENMASK(2, 0)
89 #define TX_STR_SEL GENMASK(1, 0)
98 #define PATGEN_MODE GENMASK(1, 0)
111 #define PULL_UPDN_SEL GENMASK(7, 6)
113 #define GPIO_TX_ID GENMASK(4, 0)
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H A Dmaxim-max96745.h40 #define LF_0 GENMASK(2, 0)
41 #define LF_1 GENMASK(6, 4)
44 #define LF_2 GENMASK(2, 0)
45 #define LF_3 GENMASK(6, 4)
49 #define TX_RATE GENMASK(3, 2)
62 #define VID_LINK_SEL GENMASK(2, 1)
66 #define BPP GENMASK(5, 0)
93 #define PULL_UPDN_SEL GENMASK(7, 6)
95 #define GPIO_TX_ID GENMASK(4, 0)
99 #define IO_EDGE_RATE GENMASK(6, 5)
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/rk3399_rockchip-uboot/include/
H A Dmax96755f.h18 #define DEV_ADDR GENMASK(7, 1)
25 #define TX_RATE GENMASK(3, 2)
57 #define LINK_CFG GENMASK(1, 0)
60 #define LINK_MODE GENMASK(5, 4)
70 #define TX_STR_SEL GENMASK(1, 0)
89 #define PULL_UPDN_SEL GENMASK(7, 6)
91 #define GPIO_TX_ID GENMASK(4, 0)
95 #define GPIO_RX_ID GENMASK(4, 0)
116 #define PHY_CONFIG GENMASK(2, 0)
120 #define NUM_LANES GENMASK(1, 0)
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H A Dmax96745.h26 #define TX_RATE GENMASK(3, 2)
39 #define VID_LINK_SEL GENMASK(2, 1)
50 #define PULL_UPDN_SEL GENMASK(7, 6)
52 #define GPIO_TX_ID GENMASK(4, 0)
56 #define IO_EDGE_RATE GENMASK(6, 5)
57 #define GPIO_RX_ID GENMASK(4, 0)
H A Drockchip-otp.h25 #define OTPC_USER_ADDR_MASK GENMASK(31, 16)
27 #define OTPC_USE_USER_MASK GENMASK(16, 16)
29 #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
35 #define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
36 #define SBPI_CMD_VALID_MASK GENMASK(31, 16)
42 #define SBPI_ENABLE_MASK GENMASK(16, 16)
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3368.h73 PLL_NR_MASK = GENMASK(13, 8),
75 PLL_OD_MASK = GENMASK(3, 0),
80 PLL_NF_MASK = GENMASK(12, 0),
84 PLL_BWADJ_MASK = GENMASK(11, 0),
88 PLL_MODE_MASK = GENMASK(9, 8),
94 PLL_RESET_MASK = GENMASK(5, 5),
141 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
147 MCU_CLK_DIV_MASK = GENMASK(4, 0),
151 ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6),
155 ACLK_VOP_DIV_MASK = GENMASK(4, 0),
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H A Dgrf_rk3368.h109 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
115 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
121 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
127 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
129 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
131 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
133 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
/rk3399_rockchip-uboot/include/power/
H A Dfp9931.h21 #define VPOS_VNEG_SETTING GENMASK(5, 0)
22 #define PWRON_DELAY_tDLY1 GENMASK(1, 0)
23 #define PWRON_DELAY_tDLY2 GENMASK(3, 2)
24 #define PWRON_DELAY_tDLY3 GENMASK(5, 4)
25 #define PWRON_DELAY_tDLY4 GENMASK(7, 6)
27 #define CONTROL_REG1_SS_TIME GENMASK(7, 6)
28 #define CONTROL_REG2_VN_CL GENMASK(1, 0)
29 #define CONTROL_REG2_VP_CL GENMASK(3, 2)
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_gvi.h45 #define SYS_CTRL0_LANE_NUM_MASK GENMASK(7, 4)
47 #define SYS_CTRL0_BYTE_MODE_MASK GENMASK(9, 8)
49 #define SYS_CTRL0_SECTION_NUM_MASK GENMASK(11, 10)
59 #define SYS_CTRL0_GVI_MASK GENMASK(19, 16)
74 #define SYS_CTRL1_COLOR_DEPTH_MASK GENMASK(3, 0)
88 #define SYS_CTRL2_AFIFO_READ_THOLD_MASK GENMASK(7, 0)
90 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK GENMASK(23, 16)
92 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK GENMASK(31, 24)
96 #define SYS_CTRL3_LANE0_SEL_MASK GENMASK(2, 0)
98 #define SYS_CTRL3_LANE1_SEL_MASK GENMASK(6, 4)
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H A Drk628_hdmirx.h36 #define SEL_PIXCLKSRC_MASK GENMASK(19, 18)
49 #define PREAMBLE_CNT_LIMIT_MASK GENMASK(31, 27)
51 #define OESSCTL3_THR_MASK GENMASK(20, 19)
55 #define DVI_MODE_HYST_MASK GENMASK(17, 13)
57 #define HDMI_MODE_HYST_MASK GENMASK(12, 8)
59 #define HDMI_MODE_MASK GENMASK(7, 6)
61 #define GB_DET_MASK GENMASK(5, 4)
63 #define EESS_OESS_MASK GENMASK(3, 2)
65 #define SEL_CTL01_MASK GENMASK(1, 0)
72 #define VALID_MODE_MASK GENMASK(18, 16)
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H A Drk628_combtxphy.h15 #define SW_TX_IDLE_MASK GENMASK(29, 20)
17 #define SW_TX_PD_MASK GENMASK(17, 8)
19 #define SW_BUS_WIDTH_MASK GENMASK(6, 5)
44 #define SW_PLL_CTL_CON0_MASK GENMASK(2, 0)
47 #define SW_TX_RTERM_MASK GENMASK(22, 20)
49 #define SW_TX_MODE_MASK GENMASK(17, 16)
53 #define SW_TX_CTL_CON4_MASK GENMASK(9, 8)
57 #define TX_COM_VOLT_ADJ_MASK GENMASK(2, 0)
61 #define SW_SSC_DEPTH_MASK GENMASK(7, 4)
70 #define SW_DSI_RCAL_TRIM_MASK GENMASK(27, 24)
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H A Drk628_cru.h19 #define PLL_POSTDIV1_MASK GENMASK(14, 12)
22 #define PLL_FBDIV_MASK GENMASK(11, 0)
32 #define PLL_POSTDIV2_MASK GENMASK(8, 6)
35 #define PLL_REFDIV_MASK GENMASK(5, 0)
39 #define PLL_FRAC_MASK GENMASK(23, 0)
85 #define CLK_HDMIRX_AUD_DIV_MASK GENMASK(13, 6)
87 #define CLK_HDMIRX_AUD_SEL_MASK GENMASK(15, 14)
90 #define CLK_HDMIRX_AUD_DIV_MASK GENMASK(13, 6)
93 #define CLK_HDMIRX_AUD_SEL_MASK_V1 GENMASK(15, 15)
95 #define CLK_HDMIRX_AUD_SEL_MASK_V2 GENMASK(15, 14)
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/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-edp.c18 #define EDP_PHY_TX_IDLE GENMASK(11, 8)
19 #define EDP_PHY_TX_PD GENMASK(7, 4)
23 #define EDP_PHY_PLL_DIV GENMASK(14, 0)
25 #define EDP_PHY_TX_RTERM GENMASK(10, 8)
26 #define EDP_PHY_RATE GENMASK(5, 4)
27 #define EDP_PHY_REF_DIV GENMASK(3, 0)
29 #define EDP_PHY_TX3_EMP GENMASK(15, 12)
30 #define EDP_PHY_TX2_EMP GENMASK(11, 8)
31 #define EDP_PHY_TX1_EMP GENMASK(7, 4)
32 #define EDP_PHY_TX0_EMP GENMASK(3, 0)
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H A Dphy-rockchip-samsung-hdptx.c20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
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H A Dphy-rockchip-inno-usb2.c181 mask = GENMASK(reg->bitend, reg->bitstart); in property_enable()
191 u32 mask = GENMASK(reg->bitend, reg->bitstart); in property_enabled()
753 tmp = orig & ~GENMASK(2, 0); in rk3308_usb2phy_tuning()
754 tmp |= BIT(2) & GENMASK(2, 0); in rk3308_usb2phy_tuning()
763 tmp = orig & ~GENMASK(7, 5); in rk3308_usb2phy_tuning()
764 tmp |= 0x40 & GENMASK(7, 5); in rk3308_usb2phy_tuning()
782 tmp = orig & ~GENMASK(2, 0); in rk3308_usb2phy_tuning()
783 tmp |= BIT(2) & GENMASK(2, 0); in rk3308_usb2phy_tuning()
792 tmp = orig & ~GENMASK(7, 5); in rk3308_usb2phy_tuning()
793 tmp |= 0x40 & GENMASK(7, 5); in rk3308_usb2phy_tuning()
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-meson/
H A Dsd_emmc.h34 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
38 #define CFG_BL_LEN_MASK GENMASK(7, 4)
41 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
43 #define CFG_RC_CC_MASK GENMASK(15, 12)
49 #define STATUS_MASK GENMASK(15, 0)
50 #define STATUS_ERR_MASK GENMASK(12, 0)
51 #define STATUS_RXD_ERR_MASK GENMASK(7, 0)
62 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3568/
H A Drk3568.c79 GPIO0C1_MASK = GENMASK(6, 4),
87 GPIO0C0_MASK = GENMASK(2, 0),
95 GPIO0D1_MASK = GENMASK(6, 4),
100 GPIO0D0_MASK = GENMASK(2, 0),
106 UART0_IO_SEL_MASK = GENMASK(9, 8),
115 GPIO1A1_MASK = GENMASK(6, 4),
125 GPIO1A0_MASK = GENMASK(2, 0),
136 GPIO1A6_MASK = GENMASK(10, 8),
144 GPIO1A4_MASK = GENMASK(2, 0),
153 GPIO1D6_MASK = GENMASK(10, 8),
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/rk3399_rockchip-uboot/drivers/usb/cdns3/
H A Dgadget.h227 #define USB_STS_USBSPEED_MASK GENMASK(6, 4)
310 #define USB_STS_LPMST_MASK GENMASK(19, 18)
347 #define USB_STS_LST_MASK GENMASK(29, 26)
385 #define USB_CMD_FADDR_MASK GENMASK(7, 1)
392 #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
402 #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
408 #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
417 #define USB_ITPN_MASK GENMASK(13, 0)
422 #define USB_LPM_HIRD_MASK GENMASK(3, 0)
529 #define EP_SEL_EPNO_MASK GENMASK(3, 0)
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/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3588/
H A Drk3588.c154 GPIO0B0_MASK = GENMASK(3, 0),
158 GPIO0B1_MASK = GENMASK(7, 4),
165 GPIO0C4_MASK = GENMASK(3, 0),
169 GPIO0C5_MASK = GENMASK(7, 4),
176 GPIO0B5_MASK = GENMASK(7, 4),
181 GPIO0B6_MASK = GENMASK(11, 8),
189 GPIO0D1_MASK = GENMASK(7, 4),
194 GPIO0D2_MASK = GENMASK(11, 8),
202 GPIO1A0_MASK = GENMASK(3, 0),
206 GPIO1A1_MASK = GENMASK(7, 4),
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/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126/
H A Drv1126.c116 GPIO1A7_MASK = GENMASK(14, 12),
124 GPIO1A6_MASK = GENMASK(10, 8),
132 GPIO1A5_MASK = GENMASK(6, 4),
140 GPIO1A4_MASK = GENMASK(2, 0),
147 GPIO1C3_MASK = GENMASK(14, 12),
152 GPIO1C2_MASK = GENMASK(10, 8),
157 GPIO1D5_MASK = GENMASK(6, 4),
164 GPIO1D4_MASK = GENMASK(2, 0),
171 GPIO1D1_MASK = GENMASK(6, 4),
180 GPIO1D0_MASK = GENMASK(2, 0),
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/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c23 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
24 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
27 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
28 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
31 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
32 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
139 GPIO2D1_MASK = GENMASK(3, 2), in board_debug_uart_init()
143 GPIO2D0_MASK = GENMASK(1, 0), in board_debug_uart_init()
148 GPIO2A6_MASK = GENMASK(13, 12), in board_debug_uart_init()
153 GPIO2A5_MASK = GENMASK(11, 10), in board_debug_uart_init()
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/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/rohm/
H A Drohm-bu18rl82.h291 {BU18RL82_GPIO_SEL0_LOW, GENMASK(7, 0)},
292 {BU18RL82_GPIO_SEL1_LOW, GENMASK(7, 0)},
293 {BU18RL82_GPIO_SEL2_LOW, GENMASK(7, 0)},
294 {BU18RL82_GPIO_SEL3_LOW, GENMASK(7, 0)},
295 {BU18RL82_GPIO_SEL4_LOW, GENMASK(7, 0)},
296 {BU18RL82_GPIO_SEL5_LOW, GENMASK(7, 0)},
297 {BU18RL82_GPIO_SEL6_LOW, GENMASK(7, 0)},
298 {BU18RL82_GPIO_SEL7_LOW, GENMASK(7, 0)},
302 {BU18RL82_GPIO_SEL0_HIGH, GENMASK(2, 0)},
303 {BU18RL82_GPIO_SEL1_HIGH, GENMASK(2, 0)},
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H A Drohm-bu18tl82.h341 {BU18TL82_GPIO_SEL0_LOW, GENMASK(7, 0)},
342 {BU18TL82_GPIO_SEL1_LOW, GENMASK(7, 0)},
343 {BU18TL82_GPIO_SEL2_LOW, GENMASK(7, 0)},
344 {BU18TL82_GPIO_SEL3_LOW, GENMASK(7, 0)},
345 {BU18TL82_GPIO_SEL4_LOW, GENMASK(7, 0)},
346 {BU18TL82_GPIO_SEL5_LOW, GENMASK(7, 0)},
347 {BU18TL82_GPIO_SEL6_LOW, GENMASK(7, 0)},
348 {BU18TL82_GPIO_SEL7_LOW, GENMASK(7, 0)},
352 {BU18TL82_GPIO_SEL0_HIGH, GENMASK(2, 0)},
353 {BU18TL82_GPIO_SEL1_HIGH, GENMASK(2, 0)},
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