Lines Matching refs:GENMASK
20 #define RO_REF_CLK_SEL GENMASK(11, 10)
21 #define LC_REF_CLK_SEL GENMASK(9, 8)
44 #define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4)
45 #define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0)
48 #define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3)
49 #define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0)
55 #define ROPLL_PMS_MDIV GENMASK(7, 0)
58 #define ROPLL_PMS_MDIV_AFC GENMASK(7, 0)
61 #define ANA_ROPLL_PMS_PDIV GENMASK(7, 4)
62 #define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0)
65 #define ROPLL_PMS_SDIV_RBR GENMASK(7, 4)
66 #define ROPLL_PMS_SDIV_HBR GENMASK(3, 0)
69 #define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4)
70 #define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0)
74 #define ROPLL_REF_CLK_SEL GENMASK(4, 3)
90 #define ROPLL_SDM_DENOMINATOR GENMASK(7, 0)
99 #define ROPLL_SDM_NUMERATOR GENMASK(7, 0)
102 #define ROPLL_SDC_N_RBR GENMASK(2, 0)
105 #define ROPLL_SDC_N_HBR GENMASK(5, 3)
106 #define ROPLL_SDC_N_HBR2 GENMASK(2, 0)
109 #define ROPLL_SDC_N_HBR3 GENMASK(3, 1)
112 #define ROPLL_SDC_NUMERATOR GENMASK(5, 0)
115 #define ROPLL_SDC_DENOMINATOR GENMASK(5, 0)
124 #define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0)
127 #define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2)
130 #define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3)
138 #define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0)
141 #define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5)
147 #define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0)
153 #define DP_TX_LINK_BW GENMASK(1, 0)
159 #define SSC_EN GENMASK(7, 6)
171 #define ANA_SB_RXTERM_OFFSP GENMASK(3, 0)
174 #define ANA_SB_RXTERM_OFFSN GENMASK(6, 3)
185 #define ANA_SB_TX_HLVL_PROG GENMASK(2, 0)
188 #define ANA_SB_TX_LLVL_PROG GENMASK(6, 4)
196 #define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0)
203 #define SB_RX_RCAL_OPT_CODE GENMASK(5, 4)
204 #define SB_RX_RTERM_CTRL GENMASK(3, 0)
207 #define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3)
208 #define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0)
211 #define SB_READY_DELAY_TIME GENMASK(5, 3)
212 #define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0)
215 #define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4)
218 #define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0)
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0)
224 #define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0)
228 #define SB_AFC_TOL GENMASK(3, 0)
231 #define SB_AFC_STB_NUM GENMASK(3, 0)
234 #define SB_TG_OSC_CNT_MIN GENMASK(7, 0)
237 #define SB_TG_OSC_CNT_MAX GENMASK(7, 0)
240 #define SB_PWM_AFC_CTRL GENMASK(7, 2)
254 #define DATA_BUS_WIDTH GENMASK(2, 1)
258 #define LANE_EN GENMASK(3, 0)
266 #define LN_TX_DRV_LVL_CTRL GENMASK(4, 0)
270 #define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0)
274 #define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2)
277 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5)
278 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2)
283 #define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3)
287 #define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0)
290 #define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4)
291 #define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0)
294 #define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4)
295 #define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0)
298 #define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4)
299 #define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0)
302 #define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4)
305 #define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0)
314 #define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0)
317 #define LN_ANA_TX_RESERVED GENMASK(7, 0)
1024 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0))); in rockchip_hdptx_phy_set_rate()