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/rk3399_rockchip-uboot/board/armltd/integrator/
H A DREADME2 U-Boot for ARM Integrator Development Platforms
4 Peter Pearse, ARM Ltd.
15 Each CM consists of a ARM processor core and associated hardware e.g
26 a) Run ARM boot monitor, manually run U-Boot image from flash
27 b) Run ARM boot monitor, automatically run U-Boot image from flash
30 In cases a) and b) the ARM boot monitor will have configured the CM and mapped
49 Code specific to initialization of a particular ARM processor has been placed in
53 for ARM Integrator CMs has been added
70 Integrator/AP is no longer available from ARM.
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
50 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
57 - Eight 64-bit ARM Cortex-A57 CPUs
94 The LS1012A features an advanced 64-bit ARM v8 Cortex-
100 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
101 - ARM v8 cryptography extensions
104 - ARM core-link CCI-400 cache coherent interconnect
131 - ARM generic timer
136 The LS1046A integrated multicore processor combines four ARM Cortex-A72
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S11 #define ARM(x...) macro
14 #define ARM(x...) x macro
54 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
57 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
81 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
84 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
127 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
130 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
151 ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
154 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
/rk3399_rockchip-uboot/arch/arm/cpu/
H A Du-boot.lds142 /* .ARM.exidx is sorted, so has to go in its own output section. */
143 .ARM.exidx : {
145 *(.ARM.exidx*)
149 .ARM.extab : {
151 *(.ARM.extab*)
251 .ARM.exidx : { *(.ARM.exidx*) }
H A Du-boot-spl.lds71 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A DKconfig8 bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
12 bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
/rk3399_rockchip-uboot/doc/
H A DREADME.rmobile4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
18 ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
H A DREADME.ARM-memory-map1 Subject: Re: [PATCH][CFT] bring ARM memory layout in line with the documented behaviour
14 different parts of the (ARM) code.
H A DREADME.vxworks16 For booting old kernels (6.9.x) on PowerPC and ARM, and all kernel versions
18 on PowerPC and ARM, 'bootm' shall be used.
22 VxWork 7 on PowerPC and ARM
25 mechansim (for PowerPC and ARM), thus requiring boot interface changes.
33 For ARM, the calling convention is show below:
/rk3399_rockchip-uboot/board/freescale/common/
H A DKconfig4 imply CMD_HASH if ARM
6 select SPL_BOARD_INIT if (ARM && SPL)
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A DKconfig5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
84 depends on ARM
86 Enable Freescale DDR3 controller for ARM SoCs.
121 select SYS_FSL_DDRC_ARM_GEN3 if ARM
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Du-boot-spl.lds68 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/
H A DMAINTAINERS62 ARM
68 ARM ALTERA SOCFPGA
74 ARM ATMEL AT91
80 ARM BROADCOM BCM283X
90 ARM BROADCOM BCMSTB
100 ARM FREESCALE IMX
116 ARM HISILICON
122 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
131 ARM MARVELL PXA
138 ARM RENESAS RMOBILE/R-CAR
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/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Dunified.h33 #define ARM(x...) macro
46 #define ARM(x...) x
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
66 - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
75 - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
29 - Dual high-preformance ARM Cortex-A7 cores, each core includes:
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
66 - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
75 - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
/rk3399_rockchip-uboot/board/compulab/cm_t335/
H A Du-boot.lds110 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/board/cirrus/edb93xx/
H A Du-boot.lds114 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/board/birdland/bav335x/
H A Du-boot.lds115 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/net/
H A DKconfig38 default 0x15 if ARM
45 default "U-Boot.arm" if ARM
/rk3399_rockchip-uboot/doc/SPI/
H A DREADME.sh_qspi_test5 #0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790)
6 and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dlowlevel_init.S79 @ In case of IRQ happening in Secure, then ARM will branch here.
80 @ At that moment, IRQ will be pending and ARM will jump to Non Secure
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Du-boot.lds109 .ARM.exidx : { *(.ARM.exidx*) }
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A DKconfig12 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
28 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
37 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or

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