| /rk3399_ARM-atf/drivers/st/uart/aarch64/ |
| H A D | stm32_console.S | 54 ldr w3, [x0, #USART_CR1]
55 tst w3, #USART_CR1_UE
63 ldr w3, [x0, #USART_CR1]
65 bic w3, w3, w4
66 str w3, [x0, #USART_CR1]
70 orr w3, w3, w4
71 str w3, [x0, #USART_CR1]
72 ldr w3, [x0, #USART_CR2]
74 bic w3, w3, w4
75 str w3, [x0, #USART_CR2]
[all …]
|
| /rk3399_ARM-atf/drivers/marvell/uart/ |
| H A D | a3700_console.S | 54 ldr w3, [x0, #UART_STATUS_REG]
55 and w3, w3, #UARTLSR_TXEMPTY
56 cmp w3, #0
60 mov w3, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */
62 sub w3, w3, #1
63 cmp w3, #0
74 ldr w3, [x4]
75 bic w3, w3, #MVEBU_NB_RESET_UART_N
76 str w3, [x4]
77 orr w3, w3, #MVEBU_NB_RESET_UART_N
[all …]
|
| /rk3399_ARM-atf/drivers/amlogic/console/aarch64/ |
| H A D | meson_console.S | 95 mov_imm w3, 24000000 /* TODO: This only works with a 24 MHz clock. */
96 cmp w1, w3
101 mov w3, #3
102 udiv w3, w1, w3
103 udiv w3, w3, w2
104 sub w3, w3, #1
105 orr w3, w3, #((1 << MESON_REG5_USE_XTAL_CLK_BIT) | \
107 str w3, [x0, #MESON_REG5_OFFSET]
109 ldr w3, [x0, #MESON_CONTROL_OFFSET]
110 orr w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \
[all …]
|
| /rk3399_ARM-atf/plat/mediatek/drivers/uart/ |
| H A D | 8250_console.S | 39 mov w3, #(UART_MCR_DTR | UART_MCR_RTS)
40 str w3, [x0, #UART_MCR]
43 movz w3, #:abs_g1:115200
44 movk w3, #:abs_g0_nc:115200
45 cmp w2, w3
50 mov w3, wzr
55 mov w3, #2
58 2: str w3, [x0, #UART_HIGHSPEED]
61 udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */
62 msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */
[all …]
|
| /rk3399_ARM-atf/drivers/ti/uart/aarch64/ |
| H A D | 16550_console.S | 54 ldr w3, [x0, #UARTLCR]
55 orr w3, w3, #UARTLCR_DLAB
56 str w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
60 and w3, w3, w2
61 str w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
64 mov w3, #3
65 str w3, [x0, #UARTLCR]
67 mov w3, #0
68 str w3, [x0, #UARTIER]
71 str w3, [x0, #UARTMDR1]
[all …]
|
| /rk3399_ARM-atf/plat/qti/msm8916/aarch64/ |
| H A D | uartdm_console.S | 76 ldr w3, [x1, #UART_DM_SR]
77 tbnz w3, #UART_DM_SR_TXEMT_BIT, 2f
83 mov w3, #UART_DM_CR_RESET_RX
84 str w3, [x1, #UART_DM_CR]
87 mov w3, #UART_DM_CR_RESET_TX
88 str w3, [x1, #UART_DM_CR]
96 mov w3, #UART_DM_DMEN_TX_SC
97 str w3, [x1, #UART_DM_DMEN]
100 mov w3, #UART_DM_CR_TX_ENABLE
101 str w3, [x1, #UART_DM_CR]
|
| /rk3399_ARM-atf/drivers/nxp/console/ |
| H A D | 16550_console.S | 107 ldrb w3, [x0, #UARTLCR]
108 orr w3, w3, #UARTLCR_DLAB
109 strb w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
113 and w3, w3, w2
114 strb w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
117 mov w3, #3
118 strb w3, [x0, #UARTLCR]
120 mov w3, #0
121 strb w3, [x0, #UARTIER]
123 mov w3, #(UARTFCR_FIFOEN |UARTFCR_TXCLR | UARTFCR_RXCLR)
[all …]
|
| H A D | linflex_console.S | 243 and w3, w2, #UARTSR_DTF
244 cmp w3, #0
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1046a/aarch64/ |
| H A D | ls1046a.S | 100 rev w3, w2
101 str w3, [x1, #SCFG_COREBCR_OFFSET]
107 rev w3, w2
108 orr w3, w3, w0
109 rev w2, w3
136 rev w2, w3
160 lsl w1, w3, #16
292 rev w3, w1
293 str w3, [x2, x0]
320 rev w3, w1
[all …]
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1043a/aarch64/ |
| H A D | ls1043a.S | 123 CoreMaskMsb w2, w3
130 rev w3, w2
131 str w3, [x1, #SCFG_COREBCR_OFFSET]
137 rev w3, w2
138 orr w3, w3, w0
139 rev w2, w3
180 lsl w1, w3, #16
590 ldr w3, [x4, #GICC_CTLR_OFFSET]
591 bic w3, w3, #GICC_CTLR_EN_GRP0
592 bic w3, w3, #GICC_CTLR_EN_GRP1
[all …]
|
| /rk3399_ARM-atf/drivers/arm/css/sds/aarch64/ |
| H A D | sds_helpers.S | 36 mov w3, #0
47 add w3, w3, #0x1
48 cmp w1, w3
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | plat_pmu_macros.S | 44 ldr w3, [x4, x5]
46 cmp w3, #PMU_CLST_RET
98 and w3, w1, #DDRC1_SREF_DONE_EXT
99 orr w2, w2, w3
125 and w3, w1, #DDRC1_SREF_DONE_EXT
126 orr w2, w2, w3
|
| /rk3399_ARM-atf/plat/nvidia/tegra/drivers/spe/ |
| H A D | shared_console.S | 104 mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
105 orr w2, w2, w3
114 mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
115 orr w2, w2, w3
|
| /rk3399_ARM-atf/drivers/arm/pl011/aarch64/ |
| H A D | pl011_console.S | 47 ldr w3, [x0, #UARTCR]
49 bic w3, w3, w4
50 str w3, [x0, #UARTCR]
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cpu_helpers.S | 66 and w2, w2, w3
84 and w1, w1, w3
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/ |
| H A D | ls1088a.S | 366 mov w3, #GICR_ICENABLER0_SGI15
367 str w3, [x5, #GICR_ICENABLER0_OFFSET]
388 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
389 bic w3, w3, #GICR_IGRPMODR0_SGI15
390 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
398 mov w3, #GICR_ISENABLER0_SGI15
399 str w3, [x5, #GICR_ISENABLER0_OFFSET]
897 cmp w1, w3
1677 ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
1678 orr w3, w3, w2
[all …]
|
| /rk3399_ARM-atf/plat/nxp/soc-lx2160a/aarch64/ |
| H A D | lx2160a.S | 356 mov w3, #GICR_ICENABLER0_SGI15
357 str w3, [x5, #GICR_ICENABLER0_OFFSET]
378 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
379 bic w3, w3, #GICR_IGRPMODR0_SGI15
380 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
388 mov w3, #GICR_ISENABLER0_SGI15
389 str w3, [x5, #GICR_ISENABLER0_OFFSET]
1000 bic w7, w3, w4
1017 bic w9, w3, w4
1036 bic w3, w3, w6
[all …]
|
| /rk3399_ARM-atf/drivers/cadence/uart/aarch64/ |
| H A D | cdns_console.S | 44 mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST)
45 str w3, [x0, #R_UART_CR]
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/ |
| H A D | plat_trampoline.S | 56 ldrb w3, [x1], #1
57 strb w3, [x0], #1
|
| /rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/ |
| H A D | ls1028a.S | 323 mov w3, #GICR_ICENABLER0_SGI15
324 str w3, [x5, #GICR_ICENABLER0_OFFSET]
345 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
346 bic w3, w3, #GICR_IGRPMODR0_SGI15
347 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
355 mov w3, #GICR_ISENABLER0_SGI15
356 str w3, [x5, #GICR_ISENABLER0_OFFSET]
|
| /rk3399_ARM-atf/plat/ti/common/ |
| H A D | k3_helpers.S | 150 mov w3, #0x0
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_cache.S | 40 clz w5, w3 /* bit position of #ways */
|
| /rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/ |
| H A D | xrdc_core.c | 111 static int xrdc_config_mrc_w3_w4(uint32_t mrc_con, uint32_t region, uint32_t w3, uint32_t w4) in xrdc_config_mrc_w3_w4() argument
116 mmio_write_32(w3_addr, w3); in xrdc_config_mrc_w3_w4()
|
| /rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/ |
| H A D | tegra_helpers.S | 233 ldrb w3, [x1], #1
234 strb w3, [x0], #1
|
| /rk3399_ARM-atf/lib/aarch64/ |
| H A D | misc_helpers.S | 402 ldrb w3, [x1], #1
403 strb w3, [x0], #1
|