| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_pmic_lp.c | 30 #define VCORE_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
38 #define VSRAM_CORE_TO_PMIC_VAL(volt) (((volt) - VSRAM_CORE_BASE_UV + 625 - 1) / 625) argument
150 void set_vcore_lp_volt(uint32_t volt) in set_vcore_lp_volt() argument
153 if (volt < VCORE_0_45V) in set_vcore_lp_volt()
155 if (volt > VCORE_0_75V) in set_vcore_lp_volt()
157 vcore_suspend_vol = volt; in set_vcore_lp_volt()
175 void set_vsram_lp_volt(uint32_t volt) in set_vsram_lp_volt() argument
178 if (volt > VSRAM_CORE_0_75V) in set_vsram_lp_volt()
180 vcore_sram_suspend_vol = volt; in set_vsram_lp_volt()
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| H A D | mt_spm_pmic_lp.h | 45 void set_vcore_lp_volt(unsigned int volt);
50 void set_vsram_lp_volt(uint32_t volt);
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| H A D | mt_plat_spm_setting.c | 67 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hisi_dvfs.c | 719 struct acpu_dvfs_volt_setting *volt; in acpu_dvfs_volt_init() local
735 volt = (void *)MEMORY_AXI_ACPU_FREQ_VOL_ADDR; in acpu_dvfs_volt_init()
736 volt->magic = 0x5a5ac5c5; in acpu_dvfs_volt_init()
737 volt->support_freq_num = 5; in acpu_dvfs_volt_init()
738 volt->support_freq_max = 1200000; in acpu_dvfs_volt_init()
739 volt->start_prof = 4; in acpu_dvfs_volt_init()
740 volt->vol[0] = 0x49; in acpu_dvfs_volt_init()
741 volt->vol[1] = 0x49; in acpu_dvfs_volt_init()
742 volt->vol[2] = 0x50; in acpu_dvfs_volt_init()
743 volt->vol[3] = 0x60; in acpu_dvfs_volt_init()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_pmic_lp.h | 31 void set_vsram_lp_volt(uint32_t volt);
56 static inline void set_vsram_lp_volt(uint32_t volt) in set_vsram_lp_volt() argument
58 (void)volt; in set_vsram_lp_volt()
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| H A D | mt_spm_pmic_lp.c | 169 void set_vsram_lp_volt(uint32_t volt) in set_vsram_lp_volt() argument
172 if (volt < VSRAM_CORE_0_35V || volt > VSRAM_CORE_0_75V) in set_vsram_lp_volt()
174 vcore_sram_suspend_vol = volt; in set_vsram_lp_volt()
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| H A D | mt_plat_spm_setting.c | 27 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 500 - 1) / 500) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 45 #define VOLT_TO_PMIC_VAL_66(volt) (((volt) - 50000 + 625 - 1) / 625) argument
65 #define VOLT_TO_PMIC_VAL_57(volt) (((volt) - 51875 + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | imx8ulp_psci.c | 43 .volt = (v), \
267 uint32_t volt; in imx_set_pwr_mode_cfg() local
292 if (upower_pmic_i2c_read(0x22, &volt) != 0) { in imx_set_pwr_mode_cfg()
295 pd_pmic_reg_cfgs[3].i2c_data = volt; in imx_set_pwr_mode_cfg()
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/ |
| H A D | mce_private.h | 160 uint32_t volt,
233 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
255 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| H A D | nvg.c | 233 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) in nvg_cc3_ctrl() argument
250 ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) | in nvg_cc3_ctrl()
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| H A D | ari.c | 358 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) in ari_cc3_ctrl() argument
376 ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) | in ari_cc3_ctrl()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 21 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_pmic_wrap.c | 27 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 21 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/plat/imx/imx8ulp/upower/ |
| H A D | upower_api.h | 643 int upwr_pwm_chng_reg_voltage(uint32_t reg, uint32_t volt, upwr_callb callb);
1119 int upwr_vtm_chng_pmic_voltage(uint32_t rail, uint32_t volt, upwr_callb callb);
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| H A D | upower_defs.h | 364 uint32_t volt : 12U; /* voltage value, accurate to mV, support 0~3.3V */ member
411 uint32_t volt : UPWR_HALF_ARG_BITS; /* voltage value */ member
472 upwr_pwm_volt_msg volt; /* set voltage message */ member
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| H A D | upower_api.c | 1309 int upwr_vtm_chng_pmic_voltage(uint32_t rail, uint32_t volt, upwr_callb callb) in upwr_vtm_chng_pmic_voltage() argument
1327 txmsg.args.volt = (volt + PMIC_VOLTAGE_MIN_STEP - 1U) / PMIC_VOLTAGE_MIN_STEP; in upwr_vtm_chng_pmic_voltage()
2021 int upwr_pwm_chng_reg_voltage(uint32_t reg, uint32_t volt, upwr_callb callb) in upwr_pwm_chng_reg_voltage() argument
2038 txmsg.args.volt = volt; in upwr_pwm_chng_reg_voltage()
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| H A D | upower_soc_defs.h | 801 uint32_t volt; /* Regulator voltage config */ member
824 uint32_t volt; member
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm_pmic_wrap.c | 21 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) argument
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| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | regulator.h | 52 int regulator_set_voltage(struct rdev *rdev, uint16_t volt);
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/ |
| H A D | rk3568_clk.c | 124 uint8_t volt; member
696 cpu_opp_info.volt = 50; in rockchip_clock_init()
718 gpu_opp_info.volt = 50; in rockchip_clock_init()
740 npu_opp_info.volt = 50; in rockchip_clock_init()
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| /rk3399_ARM-atf/plat/rockchip/rk3576/scmi/ |
| H A D | rk3576_clk.c | 228 uint8_t volt; member
|