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Searched refs:uint32_t (Results 1 – 25 of 1672) sorted by relevance

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/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_handoff.h25 uint32_t header_magic;
26 uint32_t header_device;
27 uint32_t _pad_0x08_0x10[2];
30 uint32_t pinmux_sel_magic;
31 uint32_t pinmux_sel_length;
32 uint32_t _pad_0x18_0x20[2];
33 uint32_t pinmux_sel_array[96]; /* offset, value */
36 uint32_t pinmux_io_magic;
37 uint32_t pinmux_io_length;
38 uint32_t _pad_0x1a8_0x1b0[2];
[all …]
H A Dsocfpga_fcs.h115 uint32_t session_id;
116 uint32_t context_id;
117 uint32_t crypto_header;
118 uint32_t size;
122 uint32_t first_word;
123 uint32_t src_addr;
124 uint32_t src_size;
125 uint32_t dst_addr;
126 uint32_t dst_size;
130 uint32_t first_word;
[all …]
/rk3399_ARM-atf/drivers/renesas/common/emmc/
H A Demmc_hal.h122 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
123 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
124 (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
125 (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
128 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
129 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
130 (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
131 (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
134 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
135 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
[all …]
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp2_ddr.h17 uint32_t mstr;
18 uint32_t mrctrl0;
19 uint32_t mrctrl1;
20 uint32_t mrctrl2;
21 uint32_t derateen;
22 uint32_t derateint;
23 uint32_t deratectl;
24 uint32_t pwrctl;
25 uint32_t pwrtmg;
26 uint32_t hwlpctl;
[all …]
H A Dstm32mp1_ddr.h16 uint32_t mstr;
17 uint32_t mrctrl0;
18 uint32_t mrctrl1;
19 uint32_t derateen;
20 uint32_t derateint;
21 uint32_t pwrctl;
22 uint32_t pwrtmg;
23 uint32_t hwlpctl;
24 uint32_t rfshctl0;
25 uint32_t rfshctl3;
[all …]
H A Dusb_dwc3.h49 uint32_t dcfg; /* @ offset 0x0 */
50 uint32_t dctl; /* @ offset 0x4 */
51 uint32_t devten; /* @ offset 0x8 */
52 uint32_t dsts; /* @ offset 0xc */
53 uint32_t dgcmdpar; /* @ offset 0x10 */
54 uint32_t dgcmd; /* @ offset 0x14 */
55 uint32_t reserved_18[2]; /* Reserved @ offset 0x18 */
56 uint32_t dalepena; /* @ offset 0x20 */
57 uint32_t reserved_24; /* @ offset 0x24 */
58 uint32_t reserved_28[54]; /* Reserved @ offset 0x28 */
[all …]
H A Dstm32mp_ddrctrl_regs.h17 uint32_t mstr ; /* 0x0 Master */
18 uint32_t stat; /* 0x4 Operating Mode Status */
20 uint32_t mrctrl0; /* 0x10 Control 0 */
21 uint32_t mrctrl1; /* 0x14 Control 1 */
22 uint32_t mrstat; /* 0x18 Status */
23 uint32_t mrctrl2; /* 0x1c Control 2 */
24 uint32_t derateen; /* 0x20 Temperature Derate Enable */
25 uint32_t derateint; /* 0x24 Temperature Derate Interval */
26 uint32_t reserved028;
27 uint32_t deratectl; /* 0x2c Temperature Derate Control */
[all …]
H A Dstm32mp1_ddr_regs.h15 uint32_t ridr; /* 0x00 R Revision Identification */
16 uint32_t pir; /* 0x04 R/W PHY Initialization */
17 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
18 uint32_t pgsr; /* 0x0C PHY General Status */
19 uint32_t dllgcr; /* 0x10 R/W DLL General Control */
20 uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
21 uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
22 uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
23 uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
24 uint32_t aciocr; /* 0x24 AC I/O Configuration */
[all …]
H A Dbsec.h43 uint32_t bsec_probe(void);
45 uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
46 uint32_t bsec_shadow_read_otp(uint32_t *val, uint32_t otp);
47 uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
48 uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
50 uint32_t bsec_read_debug_conf(void);
52 void bsec_write_scratch(uint32_t val);
55 uint32_t bsec_set_sr_lock(uint32_t otp);
56 uint32_t bsec_read_sr_lock(uint32_t otp, bool *value);
57 uint32_t bsec_set_sw_lock(uint32_t otp);
[all …]
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_phyinit_struct.h22 uint32_t dramtype; /*
32 uint32_t dimmtype; /*
40 uint32_t lp4xmode; /*
49 uint32_t numdbyte; /* Number of dbytes physically instantiated */
51 uint32_t numactivedbytedfi0; /* Number of active dbytes to be controlled by dfi0 */
53 uint32_t numactivedbytedfi1; /*
58 uint32_t numanib; /* Number of ANIBs physically instantiated */
60 uint32_t numrank_dfi0; /* Number of ranks in DFI0 channel */
62 uint32_t numrank_dfi1; /* Number of ranks in DFI1 channel (if DFI1 exists) */
64 uint32_t dramdatawidth; /*
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8173/drivers/pmic/
H A Dpmic_wrap_init.h13 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
14 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
28 uint32_t mux_sel;
29 uint32_t wrap_en;
30 uint32_t dio_en;
31 uint32_t sidly;
32 uint32_t rddmy;
33 uint32_t si_ck_con;
34 uint32_t cshext_write;
35 uint32_t cshext_read;
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dmcucfg.h14 uint32_t mp0_ca7l_cache_config;
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
19 uint32_t mp0_cache_mem_delsel0;
20 uint32_t mp0_cache_mem_delsel1;
21 uint32_t mp0_axi_config;
22 uint32_t mp0_misc_config[2];
24 uint32_t rv_addr_lw;
25 uint32_t rv_addr_hw;
27 uint32_t mp0_ca7l_cfg_dis;
[all …]
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_api_sys.h42 pl[0] = ((uint32_t)(arg0) | ((uint32_t)(flag) << 24U)); \
46 pl[1] = (uint32_t)(arg1); \
51 pl[2] = (uint32_t)(arg2); \
56 pl[3] = (uint32_t)(arg3); \
61 pl[4] = (uint32_t)(arg4); \
66 pl[5] = (uint32_t)(arg5); \
75 uint32_t latency,
76 uint32_t state,
77 uint32_t flag);
80 uint32_t latency,
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/
H A Dmce_private.h89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
90 uint32_t wake_time);
95 int32_t (*update_cstate_info)(uint32_t ari_base,
96 uint32_t cluster,
97 uint32_t ccplex,
98 uint32_t system,
100 uint32_t wake_mask,
107 int32_t (*update_crossover_time)(uint32_t ari_base,
108 uint32_t type,
109 uint32_t time);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dmcucfg.h14 uint32_t mp0_ca7l_cache_config; /* 0x0 */
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
19 uint32_t mp0_cache_mem_delsel0; /* 0x24 */
20 uint32_t mp0_cache_mem_delsel1; /* 0x28 */
21 uint32_t mp0_axi_config; /* 0x2C */
22 uint32_t mp0_misc_config[10]; /* 0x30 */
23 uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
24 uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
25 uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
[all …]
/rk3399_ARM-atf/plat/imx/common/include/
H A Dimx_snvs.h15 uint32_t hplr;
16 uint32_t hpcomr;
17 uint32_t hpcr;
18 uint32_t hpsicr;
19 uint32_t hpsvcr;
20 uint32_t hpsr;
21 uint32_t hpsvsr;
22 uint32_t hphacivr;
23 uint32_t hphacr;
24 uint32_t hprtcmr;
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram_spec_timing.h63 uint32_t mhz;
65 uint32_t tinit1;
66 uint32_t tinit2;
67 uint32_t tinit3;
68 uint32_t tinit4;
69 uint32_t tinit5;
71 uint32_t trstl;
73 uint32_t trsth;
74 uint32_t trefi;
76 uint32_t trcd;
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/pfc/D3/
H A Dpfc_init_d3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
[all …]
/rk3399_ARM-atf/include/drivers/nxp/auth/csf_hdr_parser/
H A Dcsf_hdr.h22 uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */
31 uint32_t uid_flag;
33 uint32_t psign; /* 0x10 signature offset */
34 uint32_t sign_len; /* 0x14 length of signature */
38 uint32_t sg_table_offset; /* 0x18 SG Table Offset */
39 uint32_t sg_entries; /* 0x1c no of entries in SG */
46 uint32_t img_size; /* ESBC client img size in bytes */
47 uint32_t ie_key_sel;
52 uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */
53 uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_internal.c36 uint32_t i; in __spm_output_wake_reason()
95 uint32_t con1; in spm_code_swapping()
142 uint32_t pmem_words; in __spm_kick_im_to_fetch()
143 uint32_t total_words; in __spm_kick_im_to_fetch()
144 uint32_t pmem_start; in __spm_kick_im_to_fetch()
145 uint32_t dmem_start; in __spm_kick_im_to_fetch()
146 uint32_t ptr; in __spm_kick_im_to_fetch()
181 uint32_t resource_usage) in __spm_set_power_control()
201 (((uint32_t)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | in __spm_set_power_control()
202 (((uint32_t)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | in __spm_set_power_control()
[all …]
/rk3399_ARM-atf/drivers/arm/mhu/
H A Dmhu_v3_x_private.h26 const volatile uint32_t pbx_blk_id;
30 const volatile uint32_t pbx_feat_spt0;
32 const volatile uint32_t pbx_feat_spt1;
36 const volatile uint32_t pbx_dbch_cfg0;
40 const volatile uint32_t pbx_ffch_cfg0;
44 const volatile uint32_t pbx_fch_cfg0;
48 volatile uint32_t pbx_ctrl;
55 const volatile uint32_t pbx_dbch_int_st[4];
60 const volatile uint32_t pbx_ffch_int_st[2];
64 const volatile uint32_t pbx_iidr;
[all …]
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_api_sys.h25 enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
26 uint32_t x2, uint32_t x3, uint32_t x4,
27 uint32_t x5, uint32_t *result);
28 enum pm_ret_status pm_self_suspend(uint32_t nid,
29 uint32_t latency,
30 uint32_t state,
31 uintptr_t address, uint32_t flag);
32 enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address,
33 uintptr_t address, uint8_t ack, uint32_t flag);
34 enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device,
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/ddr/
H A Dddr_rk3368.c36 uint32_t ddrfreq;
37 uint32_t TOGCNT1U;
38 uint32_t TINIT;
39 uint32_t TRSTH;
40 uint32_t TOGCNT100N;
41 uint32_t TREFI;
42 uint32_t TMRD;
43 uint32_t TRFC;
44 uint32_t TRP;
45 uint32_t TRTW;
[all …]
/rk3399_ARM-atf/plat/st/stm32mp2/include/
H A Dboot_api.h224 uint32_t chip_ver;
227 uint32_t cut_ver;
230 uint32_t rom_mask_ver;
233 uint32_t bootrom_ver;
236 uint32_t for_chip_design_rtl_ver;
239 uint32_t platform_type_ver;
253 uint32_t boot_partition_used_toboot;
255 uint32_t reserved1[3];
264 uint32_t sd_err_internal_timeout_cnt;
265 uint32_t sd_err_dcrc_fail_cnt;
[all …]
/rk3399_ARM-atf/drivers/renesas/rzg/pfc/G2N/
H A Dpfc_init_g2n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
[all …]

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