Lines Matching refs:uint32_t
49 uint32_t dcfg; /* @ offset 0x0 */
50 uint32_t dctl; /* @ offset 0x4 */
51 uint32_t devten; /* @ offset 0x8 */
52 uint32_t dsts; /* @ offset 0xc */
53 uint32_t dgcmdpar; /* @ offset 0x10 */
54 uint32_t dgcmd; /* @ offset 0x14 */
55 uint32_t reserved_18[2]; /* Reserved @ offset 0x18 */
56 uint32_t dalepena; /* @ offset 0x20 */
57 uint32_t reserved_24; /* @ offset 0x24 */
58 uint32_t reserved_28[54]; /* Reserved @ offset 0x28 */
59 uint32_t depcmdpar2; /* @ offset 0x100 */
60 uint32_t depcmdpar1; /* @ offset 0x104 */
61 uint32_t depcmdpar0; /* @ offset 0x108 */
62 uint32_t depcmd; /* @ offset 0x10c */
63 uint32_t reserved_110[124];/* Reserved @ offset 0x110 */
64 uint32_t dev_imod; /* @ offset 0x300 */
65 uint32_t reserved_304[0xfc / 4]; /* Reserved @ offset 0x304 */
69 uint32_t gsbuscfg0; /* @ offset 0x0 */
70 uint32_t gsbuscfg1; /* @ offset 0x4 */
71 uint32_t gtxthrcfg; /* @ offset 0x8 */
72 uint32_t grxthrcfg; /* @ offset 0xc */
73 uint32_t gctl; /* @ offset 0x10 */
74 uint32_t gpmsts; /* @ offset 0x14 */
75 uint32_t gsts; /* @ offset 0x18 */
76 uint32_t guctl1; /* @ offset 0x1c */
77 uint32_t gsnpsid; /* @ offset 0x20 */
78 uint32_t ggpio; /* @ offset 0x24 */
79 uint32_t guid; /* @ offset 0x28 */
80 uint32_t guctl; /* @ offset 0x2c */
81 uint32_t gbuserraddrlo; /* @ offset 0x30 */
82 uint32_t gbuserraddrhi; /* @ offset 0x34 */
83 uint32_t gprtbimaplo; /* @ offset 0x38 */
84 uint32_t gprtbimaphi; /* @ offset 0x3c */
85 uint32_t ghwparams0; /* @ offset 0x40 */
86 uint32_t ghwparams1; /* @ offset 0x44 */
87 uint32_t ghwparams2; /* @ offset 0x48 */
88 uint32_t ghwparams3; /* @ offset 0x4c */
89 uint32_t ghwparams4; /* @ offset 0x50 */
90 uint32_t ghwparams5; /* @ offset 0x54 */
91 uint32_t ghwparams6; /* @ offset 0x58 */
92 uint32_t ghwparams7; /* @ offset 0x5c */
93 uint32_t gdbgfifospace; /* @ offset 0x60 */
94 uint32_t gdbgltssm; /* @ offset 0x64 */
95 uint32_t gdbglnmcc; /* @ offset 0x68 */
96 uint32_t gdbgbmu; /* @ offset 0x6c */
97 uint32_t gdbglspmux_hst; /* @ offset 0x70 */
98 uint32_t gdbglsp; /* @ offset 0x74 */
99 uint32_t gdbgepinfo0; /* @ offset 0x78 */
100 uint32_t gdbgepinfo1; /* @ offset 0x7c */
101 uint32_t gprtbimap_hslo; /* @ offset 0x80 */
102 uint32_t gprtbimap_hshi; /* @ offset 0x84 */
103 uint32_t gprtbimap_fslo; /* @ offset 0x88 */
104 uint32_t gprtbimap_fshi; /* @ offset 0x8c */
105 uint32_t reserved_90; /* Reserved @ offset 0x90 */
106 uint32_t reserved_94; /* @ offset 0x94 */
107 uint32_t reserved_98; /* @ offset 0x98 */
108 uint32_t guctl2; /* @ offset 0x9c */
109 uint32_t reserved_A0[24]; /* Reserved @ offset 0xa0 */
110 uint32_t gusb2phycfg; /* @ offset 0x100 */
111 uint32_t reserved_104[15]; /* Reserved @ offset 0x104 */
112 uint32_t gusb2i2cctl; /* @ offset 0x140 */
113 uint32_t reserved_144[15]; /* Reserved @ offset 0x144 */
114 uint32_t gusb2phyacc_ulpi; /* @ offset 0x180 */
115 uint32_t reserved_184[15]; /* Reserved @ offset 0x184 */
116 uint32_t gusb3pipectl; /* @ offset 0x1c0 */
117 uint32_t reserved_1c4[15]; /* Reserved @ offset 0x1c4 */
118 uint32_t gtxfifosiz0; /* @ offset 0x200 */
119 uint32_t gtxfifosiz1; /* @ offset 0x204 */
120 uint32_t gtxfifosiz2; /* @ offset 0x208 */
121 uint32_t gtxfifosiz3; /* @ offset 0x20c */
122 uint32_t gtxfifosiz4; /* @ offset 0x210 */
123 uint32_t gtxfifosiz5; /* @ offset 0x214 */
124 uint32_t gtxfifosiz6; /* @ offset 0x218 */
125 uint32_t gtxfifosiz7; /* @ offset 0x21c */
126 uint32_t gtxfifosiz8; /* @ offset 0x220 */
127 uint32_t gtxfifosiz9; /* @ offset 0x224 */
128 uint32_t gtxfifosiz10; /* @ offset 0x228 */
129 uint32_t gtxfifosiz11; /* @ offset 0x22c */
130 uint32_t reserved_230[20]; /* Reserved @ offset 0x230 */
131 uint32_t grxfifosiz0; /* @ offset 0x280 */
132 uint32_t grxfifosiz1; /* @ offset 0x284 */
133 uint32_t grxfifosiz2; /* @ offset 0x288 */
134 uint32_t reserved_28c[29]; /* Reserved @ offset 0x28c */
135 uint32_t gevntadrlo; /* @ offset 0x300 */
136 uint32_t gevntadrhi; /* @ offset 0x304 */
137 uint32_t gevntsiz; /* @ offset 0x308 */
138 uint32_t gevntcount; /* @ offset 0x30c */
139 uint32_t reserved_310[124]; /* Reserved @ offset 0x310 */
140 uint32_t ghwparams8; /* @ offset 0x500 */
141 uint32_t reserved_504[3]; /* Reserved @ offset 0x504 */
142 uint32_t gtxfifopridev; /* @ offset 0x510 */
143 uint32_t reserved_514; /* Reserved @ offset 0x514 */
144 uint32_t gtxfifoprihst; /* @ offset 0x518 */
145 uint32_t grxfifoprihst; /* @ offset 0x51c */
146 uint32_t reserved_520; /* Reserved @ offset 0x520 */
147 uint32_t gdmahlratio; /* @ offset 0x524 */
148 uint32_t reserved_528[2]; /* Reserved @ offset 0x528 */
149 uint32_t gfladj; /* @ offset 0x530 */
150 uint32_t reserved_534[0xcc / 4]; /* Reserved @ offset 0x534 */
154 uint32_t bpl; /* Buffer Pointer Low Address */
155 uint32_t bph; /* Buffer Pointer High Address */
156 uint32_t size; /* Buffer Size */
157 uint32_t ctrl; /* Control and Status field */
181 uint32_t xfer_dest_len;
200 uint32_t evtbufferpos[USB_DWC3_INT_INUSE]; /*!< Read Position inside the Event Buffer */