Searched refs:stm32mp_rcc_base (Results 1 – 13 of 13) sorted by relevance
233 return (mmio_read_32(stm32mp_rcc_base() + RCC_R104CIDCFGR) & RCC_R104CIDCFGR_CFEN) == in is_ddr_cid_filtering_enabled()239 mmio_setbits_32(stm32mp_rcc_base() + RCC_R104CIDCFGR, RCC_R104CIDCFGR_CFEN); in ddr_enable_cid_filtering()241 mmio_setbits_32(stm32mp_rcc_base() + RCC_R104SEMCR, RCC_R104SEMCR_SEM_MUTEX); in ddr_enable_cid_filtering()252 saved_sem_mutex = mmio_read_32(stm32mp_rcc_base() + RCC_R104SEMCR) & in ddr_disable_cid_filtering()254 mmio_clrbits_32(stm32mp_rcc_base() + RCC_R104CIDCFGR, RCC_R104CIDCFGR_CFEN); in ddr_disable_cid_filtering()279 uintptr_t rcc_base = stm32mp_rcc_base(); in sr_ssr_entry()334 uintptr_t rcc_base = stm32mp_rcc_base(); in sr_ssr_exit()367 mmio_clrsetbits_32(stm32mp_rcc_base() + RCC_DDRITFCFGR, in sr_hsr_set()391 mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN); in sr_hsr_entry()398 mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, in sr_hsr_exit()[all …]
16 mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, in ddr_enable_clock()
148 priv->rcc = stm32mp_rcc_base(); in stm32mp1_ddr_probe()
201 priv->rcc = stm32mp_rcc_base(); in stm32mp2_ddr_probe()
33 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_assert()54 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_deassert()73 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_system_reset()
33 uintptr_t rcc_base = stm32mp_rcc_base(); in reset_toggle()68 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_system_reset()
931 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_secure()939 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_mckprot()996 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_clk_get_parent()1034 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); in stm32mp1_pll_get_fref()1050 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_get_fvco()1093 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()1105 uintptr_t rcc_base = stm32mp_rcc_base(); in get_clock_rate()1306 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_enable()1322 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_disable()1341 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_is_enabled()[all …]
1084 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_set_hsidiv()
48 uintptr_t stm32mp_rcc_base(void);
39 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); in print_reset_reason()116 uintptr_t rcc_base = stm32mp_rcc_base(); in reset_backup_domain()
104 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32_pwr_domain_on_finish()
56 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); in print_reset_reason()234 rcc_base = stm32mp_rcc_base(); in bl2_plat_arch_setup()
112 uintptr_t stm32mp_rcc_base(void) in stm32mp_rcc_base() function