| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | imx_rdc.h | 55 union rdc_setting setting; member 59 {RDC_MDA, (i), .setting.rdc_mda = (mda), } 61 {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), } 65 .setting.rdc_mem_region[0] = (msa), \ 66 .setting.rdc_mem_region[1] = (mea), \ 67 .setting.rdc_mem_region[2] = (mrc), \
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| /rk3399_ARM-atf/plat/imx/imx8m/ |
| H A D | imx_rdc.c | 64 rdc->setting.rdc_pdap = D0R | D0W; in imx_rdc_console_access_enable() 80 mmio_write_32(MDAn(rdc->index), rdc->setting.rdc_mda); in imx_rdc_init() 84 mmio_write_32(PDAPn(rdc->index), rdc->setting.rdc_pdap); in imx_rdc_init() 88 mmio_write_32(MRSAn(rdc->index), rdc->setting.rdc_mem_region[0]); in imx_rdc_init() 89 mmio_write_32(MREAn(rdc->index), rdc->setting.rdc_mem_region[1]); in imx_rdc_init() 90 mmio_write_32(MRCn(rdc->index), rdc->setting.rdc_mem_region[2]); in imx_rdc_init()
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-7.rst | 42 world execution. The mitigation is enabled by setting an implementation defined 65 - Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of 68 - Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the 71 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1`` 100 - Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of
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| H A D | security-advisory-tfv-13.rst | 73 setting CPUACTLR6_EL1[41] = 1. For C1-Pro, the affected prefetcher is 74 instead disabled by setting IMP_CPUECTLR_EL1[49] = 1.
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| H A D | security-advisory-tfv-3.rst | 67 non-executable by setting the ``SCTLR_ELx.WXN`` bit. This overrides any value 81 mapped into the secure world is non-executable by setting the ``SCR_EL3.SIF``
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| H A D | security-advisory-tfv-12.rst | 75 official advisory. The issue is avoided by setting CPUECTLR_EL1[46] to 1 which will
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| /rk3399_ARM-atf/docs/_static/css/ |
| H A D | custom.css | 9 * With this setting sequences of whitespace inside
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| /rk3399_ARM-atf/docs/design_documents/ |
| H A D | cmake_framework.rst | 64 The related parameters shall be packed into a group (or "setting group"). The 65 setting groups shall be defined and filled with content in config files. 76 extends the built-in functionality, it can use the setting groups described in 121 First, we create a setting group called *mem_conf* and fill it with several 126 Next, we create a target called *fw1* and add the *mem_conf* setting group to 128 the parameters declared in the setting group. Then we set the target type to
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| /rk3399_ARM-atf/docs/plat/arm/ |
| H A D | arm-build-options.rst | 9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The 76 ``HASH_ALG`` is not specified. A different RSA key can be specified by setting 87 be changed by setting ``ROT_KEY``, there are 3k and 4k RSA keys in
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| /rk3399_ARM-atf/docs/plat/ |
| H A D | imx8m.rst | 53 When setting NEED_BL2=1 on imx8mm. We support an alternative way of 67 When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs
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| H A D | rpi4.rst | 66 To accommodate this existing way of configuring and setting up the board, 74 setting them in ``config.txt``. If the GPU firmware finds a magic value in the
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| H A D | rpi5.rst | 62 with ``PRELOADED_BL33_BASE`` or ``RPI3_PRELOADED_DTB_BASE``, setting those config
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| H A D | rcar-gen3.rst | 208 NOTICE: AVS setting succeeded. DVFS_SetVID=0x53 211 NOTICE: BL2: QoS is default setting(rev.0.37)
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| H A D | allwinner.rst | 69 This setting defaults to 1. In some situations that enables too many
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| H A D | rz-g2.rst | 184 NOTICE: BL2: QoS is default setting(rev.0.19)
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| /rk3399_ARM-atf/docs/ |
| H A D | architecture_features.rst | 469 When setting the flag to 0, the feature is disabled during compilation, and the 544 worlds by setting/clearing the bit in the context copy of this register. 567 setting it to ``2`` (``FEAT_STATE_CHECKED``).
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| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | arisc_off.S | 26 # - Using that mask, activate the core output clamps by setting the
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| /rk3399_ARM-atf/docs/plat/nxp/ |
| H A D | nxp-ls-tbbr.rst | 47 - Enable this option by setting ``NXP_TBBR_USE_X509=1`` on the make command line.
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| /rk3399_ARM-atf/docs/components/ |
| H A D | romlib-design.rst | 145 :ref:`Performing an Initial Build` for more information about setting this
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| H A D | platform-interrupt-controller-API.rst | 252 inserts barrier to make memory updates visible before setting interrupt pending,
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| H A D | exception-handling.rst | 17 The |EHF| is selected by setting the build option ``EL3_EXCEPTION_HANDLING`` to 537 interrupts. This also results in setting the routing bits in ``SCR_EL3``.
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| H A D | granule-protection-tables-design.rst | 181 setting the correct register values.
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| /rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/ |
| H A D | ddrc.c | 181 #error Invalid setting for DDRC_NUM_CS
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| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | 358 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 393 This lockdown is established by setting individual trap bits for 408 Dirty state tracking structure) by setting ``SCR_EL3.HDBSSEn`` for NS world. 414 HACDBS (Hardware accelerator for cleaning Dirty state) by setting 545 (Translation Hardening Extension) at EL2 and below, setting the bit 553 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 561 setting ``MDCR_EL3.EnSTEPOP`` so that lower ELs can access ``MDSTEPOP_EL1``. 567 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 1506 Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1578 ``ENABLE_FEAT_RME``. Until deprecated, setting this option to 1, will also
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| /rk3399_ARM-atf/docs/design/ |
| H A D | console-framework.rst | 42 scope or multiple scopes. In single scope for example, setting three different
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