13d660799SJacky Bai /* 2d76f012eSJacky Bai * Copyright (c) 2019-2022 NXP. All rights reserved. 33d660799SJacky Bai * 43d660799SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 53d660799SJacky Bai */ 63d660799SJacky Bai 73d660799SJacky Bai #ifndef IMX_RDC_H 83d660799SJacky Bai #define IMX_RDC_H 93d660799SJacky Bai 103d660799SJacky Bai #include <lib/utils_def.h> 113d660799SJacky Bai 12d76f012eSJacky Bai #include <imx_sec_def.h> 133d660799SJacky Bai #include <platform_def.h> 143d660799SJacky Bai 153d660799SJacky Bai #define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4) 163d660799SJacky Bai #define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4) 1797600cb5SJacky Bai #define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10) 1897600cb5SJacky Bai #define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10) 1997600cb5SJacky Bai #define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10) 203d660799SJacky Bai 213d660799SJacky Bai #define LCK BIT(31) 223d660799SJacky Bai #define SREQ BIT(30) 233d660799SJacky Bai #define ENA BIT(30) 243d660799SJacky Bai 253d660799SJacky Bai #define DID0 U(0x0) 263d660799SJacky Bai #define DID1 U(0x1) 273d660799SJacky Bai #define DID2 U(0x2) 283d660799SJacky Bai #define DID3 U(0x3) 293d660799SJacky Bai 303d660799SJacky Bai #define D3R BIT(7) 313d660799SJacky Bai #define D3W BIT(6) 323d660799SJacky Bai #define D2R BIT(5) 333d660799SJacky Bai #define D2W BIT(4) 343d660799SJacky Bai #define D1R BIT(3) 353d660799SJacky Bai #define D1W BIT(2) 363d660799SJacky Bai #define D0R BIT(1) 373d660799SJacky Bai #define D0W BIT(0) 383d660799SJacky Bai 393d660799SJacky Bai union rdc_setting { 403d660799SJacky Bai uint32_t rdc_mda; /* Master Domain Assignment */ 413d660799SJacky Bai uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */ 423d660799SJacky Bai uint32_t rdc_mem_region[3]; /* Memory Region Access Control */ 433d660799SJacky Bai }; 443d660799SJacky Bai 453d660799SJacky Bai enum rdc_type { 463d660799SJacky Bai RDC_INVALID, 473d660799SJacky Bai RDC_MDA, 483d660799SJacky Bai RDC_PDAP, 493d660799SJacky Bai RDC_MEM_REGION, 503d660799SJacky Bai }; 513d660799SJacky Bai 523d660799SJacky Bai struct imx_rdc_cfg { 533d660799SJacky Bai enum rdc_type type; /* config type Master, Peripheral or Memory region */ 543d660799SJacky Bai int index; 553d660799SJacky Bai union rdc_setting setting; 563d660799SJacky Bai }; 573d660799SJacky Bai 583d660799SJacky Bai #define RDC_MDAn(i, mda) \ 593d660799SJacky Bai {RDC_MDA, (i), .setting.rdc_mda = (mda), } 603d660799SJacky Bai #define RDC_PDAPn(i, pdap) \ 613d660799SJacky Bai {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), } 623d660799SJacky Bai 633d660799SJacky Bai #define RDC_MEM_REGIONn(i, msa, mea, mrc) \ 643d660799SJacky Bai { RDC_MEM_REGION, (i), \ 653d660799SJacky Bai .setting.rdc_mem_region[0] = (msa), \ 663d660799SJacky Bai .setting.rdc_mem_region[1] = (mea), \ 673d660799SJacky Bai .setting.rdc_mem_region[2] = (mrc), \ 683d660799SJacky Bai } 693d660799SJacky Bai 70*f7434fa1SDario Binacchi void imx_rdc_init(struct imx_rdc_cfg *cfg, unsigned int console_base); 713d660799SJacky Bai 723d660799SJacky Bai #endif /* IMX_RDC_H */ 733d660799SJacky Bai 74