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/rk3399_ARM-atf/plat/mediatek/lib/mtk_init/
H A Dmtk_init.c19 void mtk_init_one_level(uint32_t level) in mtk_init_one_level() argument
24 if (level >= MTK_INIT_LVL_MAX) { in mtk_init_one_level()
25 ERROR("invalid level:%u\n", level); in mtk_init_one_level()
29 INFO("init calling level:%u\n", level); in mtk_init_one_level()
30 for (entry = initcall_list[level]; in mtk_init_one_level()
31 (entry != NULL) && (entry < initcall_list[level + 1]); in mtk_init_one_level()
/rk3399_ARM-atf/plat/common/
H A Dplat_log_common.c18 unsigned int level; in plat_log_get_prefix() local
21 level = LOG_LEVEL_ERROR; in plat_log_get_prefix()
23 level = LOG_LEVEL_VERBOSE; in plat_log_get_prefix()
25 level = log_level; in plat_log_get_prefix()
28 return plat_prefix_str[(level / 10U) - 1U]; in plat_log_get_prefix()
/rk3399_ARM-atf/lib/xlat_tables_v2/
H A Dxlat_tables_utils.c142 unsigned int level) in xlat_tables_print_internal() argument
144 assert(level <= XLAT_TABLE_LEVEL_MAX); in xlat_tables_print_internal()
149 size_t level_size = XLAT_BLOCK_SIZE(level); in xlat_tables_print_internal()
167 level_spacers[level], in xlat_tables_print_internal()
176 level_spacers[level], in xlat_tables_print_internal()
187 (level < XLAT_TABLE_LEVEL_MAX)) { in xlat_tables_print_internal()
195 level_spacers[level], in xlat_tables_print_internal()
202 XLAT_TABLE_ENTRIES, level + 1U); in xlat_tables_print_internal()
205 level_spacers[level], table_idx_va, in xlat_tables_print_internal()
219 level_spacers[level], invalid_row_count - 1); in xlat_tables_print_internal()
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H A Dxlat_tables_core.c110 unsigned long long addr_pa, unsigned int level) in xlat_desc() argument
117 assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U); in xlat_desc()
124 desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; in xlat_desc()
264 const unsigned int level) in xlat_tables_find_start_va() argument
270 table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level); in xlat_tables_find_start_va()
284 const unsigned int level) in xlat_tables_va_to_index() argument
286 return (unsigned int)((va - table_base_va) >> XLAT_ADDR_SHIFT(level)); in xlat_tables_va_to_index()
297 const unsigned int level, const uint64_t desc_type) in xlat_tables_unmap_region_action() argument
306 if (level == 3U) { in xlat_tables_unmap_region_action()
341 assert(level < 3U); in xlat_tables_unmap_region_action()
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/rk3399_ARM-atf/include/lib/xlat_tables/
H A Dxlat_tables_defs.h101 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ argument
102 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
104 #define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) argument
106 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) argument
108 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) argument
113 #define XLAT_TABLE_IDX(virtual_addr, level) \ argument
114 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
/rk3399_ARM-atf/lib/xlat_tables/
H A Dxlat_tables_common.c29 #define get_level_spacer(level) \ argument
30 (((level) == U(0)) ? LVL0_SPACER : \
31 (((level) == U(1)) ? LVL1_SPACER : \
32 (((level) == U(2)) ? LVL2_SPACER : LVL3_SPACER)))
190 unsigned int level) in mmap_desc() argument
196 assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U); in mmap_desc()
203 desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; in mmap_desc()
327 unsigned int level) in init_xlation_table_inner() argument
329 assert((level >= XLAT_TABLE_LEVEL_MIN) && in init_xlation_table_inner()
330 (level <= XLAT_TABLE_LEVEL_MAX)); in init_xlation_table_inner()
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H A Dxlat_tables_private.h38 unsigned int level, uintptr_t *max_va,
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-n1sdp.rst21 ``CPU_SUSPEND`` to deepest power level
23 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in parallel (v2.14)
37 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in parallel (v2.13)
51 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in serial (v2.14)
65 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in serial (v2.13)
79 ``CPU_SUSPEND`` to power level 0
82 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in parallel (v2.14)
96 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in parallel (v2.13)
110 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in serial (v2.14)
124 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in serial (v2.13)
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H A Dpsci-performance-juno.rst46 ``CPU_SUSPEND`` to deepest power level
49 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
68 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
87 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
106 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
125 ``CPU_SUSPEND`` to power level 0
128 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
147 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
166 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.14)
185 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
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/rk3399_ARM-atf/lib/psci/
H A Dpsci_setup.c47 unsigned char level) in psci_init_pwr_domain_node() argument
49 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()
52 psci_non_cpu_pd_nodes[node_idx].level = level; in psci_init_pwr_domain_node()
138 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree() local
149 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
168 (unsigned char)level); in populate_power_domain_tree()
176 level--; in populate_power_domain_tree()
179 if (level == (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
H A Dpsci_common.c833 unsigned int level; in psci_acquire_pwr_domain_locks() local
836 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { in psci_acquire_pwr_domain_locks()
837 parent_idx = parent_nodes[level - 1U]; in psci_acquire_pwr_domain_locks()
851 unsigned int level; in psci_release_pwr_domain_locks() local
854 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { in psci_release_pwr_domain_locks()
855 parent_idx = parent_nodes[level - 1U]; in psci_release_pwr_domain_locks()
1167 psci_non_cpu_pd_nodes[idx].level, in psci_print_power_domain_map()
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Da3700_ea.c26 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_ea_handler() local
63 if (level < MODE_EL3 && ea_reason == ERROR_EA_ASYNC && in plat_ea_handler()
68 syndrome, read_mpidr_el1(), get_el_str(level)); in plat_ea_handler()
/rk3399_ARM-atf/plat/brcm/board/common/
H A Dbcm_elog.c39 unsigned int level; member
98 int bcm_elog_init(void *base, uint32_t size, unsigned int level) in bcm_elog_init() argument
106 elog->level = level / 10; in bcm_elog_init()
196 unsigned int level = fmt[0]; in bcm_elog() local
198 if (!elog->is_active || level > elog->level) in bcm_elog()
201 prefix_str = plat_log_get_prefix(level); in bcm_elog()
/rk3399_ARM-atf/lib/xlat_tables/aarch32/
H A Dnonlpae_tables.c293 unsigned int level) in mmap_desc() argument
297 switch (level) { in mmap_desc()
335 if (level == 2U) { in mmap_desc()
397 unsigned int level) in init_xlation_table_inner() argument
399 unsigned int level_size_shift = (level == 1U) ? in init_xlation_table_inner()
402 unsigned int level_index_mask = (level == 1U) ? in init_xlation_table_inner()
406 assert((level == 1U) || (level == 2U)); in init_xlation_table_inner()
408 VERBOSE("init xlat table at %p (level%1u)\n", (void *)table, level); in init_xlation_table_inner()
420 if (level == 2U) { in init_xlation_table_inner()
421 printf(" 0x%lx %x " + 6 - 2 * level, in init_xlation_table_inner()
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/rk3399_ARM-atf/include/plat/brcm/common/
H A Dbcm_elog.h15 int bcm_elog_init(void *base, uint32_t size, unsigned int level);
21 unsigned int level) in bcm_elog_init() argument
/rk3399_ARM-atf/lib/zlib/
H A Dzlib.h714 int level,
1268 int level);
1403 ZEXTERN int ZEXPORT gzsetparams(gzFile file, int level, int strategy);
1803 ZEXTERN int ZEXPORT deflateInit_(z_streamp strm, int level,
1807 ZEXTERN int ZEXPORT deflateInit2_(z_streamp strm, int level, int method,
1818 # define z_deflateInit(strm, level) \ argument
1819 deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))
1822 # define z_deflateInit2(strm, level, method, windowBits, memLevel, strategy) \ argument
1823 deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\
1832 # define deflateInit(strm, level) \ argument
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/rk3399_ARM-atf/plat/arm/board/fvp/aarch64/
H A Dfvp_ea.c35 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_ea_handler() local
39 if ((level < MODE_EL3) && (fault_address == TEST_ADDRESS)) { in plat_ea_handler()
/rk3399_ARM-atf/fdts/
H A Da5ds.dts30 next-level-cache = <&L2>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
61 cache-level = <2>;
/rk3399_ARM-atf/plat/common/aarch64/
H A Dplat_common.c103 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_default_ea_handler() local
107 read_mpidr_el1(), get_el_str(level)); in plat_default_ea_handler()
/rk3399_ARM-atf/docs/components/
H A Dexception-handling.rst98 for more than one priority level.
107 A priority level is *active* when a handler at that priority level is currently
111 The priority level is likewise implicitly deactivated when the interrupt
118 activate and deactivate the respective priority level as and when they're
126 explicit. The |EHF| therefore disallows for lower priority level to be activated
127 whilst a higher priority level is active, and would result in a panic.
129 level when a higher priority level is active.
131 In essence, priority level activation and deactivation conceptually works like a
143 top-level handler for interrupts that target EL3, as described in the
168 handlers for them. A given priority level can be assigned to only one handler. A
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H A Dxlat-tables-lib-v2-design.rst17 translation regime than the exception level the library code is executing at;
79 The granularity controls the translation table level to go down to when mapping
84 - using a single level-2 translation table entry;
85 - using a level-2 intermediate entry to a level-3 translation table (which
91 page tables to refine the mappings. If a single level-2 entry has been used
92 here, a level-3 table will need to be allocated on the fly and the level-2
93 modified to point to this new level-3 table. This has a performance cost at
109 translation regime than the exception level the library code is executing at.
118 to the translation regime of the current exception level. Additional contexts
139 excluding the initial lookup level translation table, which is always
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H A Dgranule-protection-tables-design.rst46 The GPT can function as either a 1 level or 2 level lookup depending on how a
47 PAS region is configured. The first step is the level 0 table, each entry in the
48 level 0 table controls access to a relatively large region in memory (GPT Block
50 mapping is used. Level 0 entry can also link to a level 1 table (GPT Table
67 which is how large each level 1 granule is, and L0GPTSZ (level 0 GPT size) which
68 determines how much physical memory is governed by each level 0 entry. A granule
127 building the level 0 tables.
130 building the level 1 tables which are linked from level 0 descriptors. The
132 its level 0 table in SRAM and its level 1 table(s) in DRAM.
171 #. Firmware must call ``gpt_init_l0_tables`` to initialize the level 0 tables to
/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Dimx8m_csu.h63 #define CSU_CSLx(i, level, lk) \ argument
64 {CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
/rk3399_ARM-atf/docs/getting_started/
H A Dimage-terminology.rst22 - Previously, the format for 3rd level images had 2 forms; ``BL3`` was either
65 required to load and authenticate all 3rd level firmware images into their
82 abbreviation should be avoided; use the recommended **Other AP 3rd level
90 Other AP 3rd level images: ``AP_BL3_XXX``
93 The abbreviated names of the existing 3rd level images imply a load/execution
97 but new 3rd level images should be suffixed with an underscore followed by text
100 In systems where 3rd level images are provided by different vendors, the
132 SCP needs to load/authenticate multiple 3rd level images in future.
153 secure and normal world. The "level" of the BL image is relative to the world
184 underscore and the level of the firmware image.
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst26 over the sibling nodes at a particular level to find a specified power
28 a 'start' to an 'end' power level. The binary search is required to find the
29 node at each level. The natural way to perform this traversal is to
31 level.
58 highest power level implemented in the platform. This caters for platforms
60 the FVP has two cluster power domains at the highest level (1).
69 to consider at the next level. The sum of the values (number of children) of
70 all the entries at a level specifies the number of entries in the array for
71 the next level.
192 * Index of the first CPU power domain node level 0 which has this node
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