docs/perf/psci-performance-juno.rst

46 ``CPU_SUSPEND`` to deepest power level
49 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
68 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
87 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
106 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
125 ``CPU_SUSPEND`` to power level 0
128 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
147 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
166 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.14)
185 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
207 core to the deepest power level.
298 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
330 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
349 There is no lock contention in TF generic code at power level 0 but the large
360 require locks at power level 0.
363 the cache associated with power level 0 is flushed (L1).
365 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
386 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
395 level 0, which only requires L1 cache flush.
397 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
417 only necessary to flush the cache to power level 0 (L1). This is the best case
427 ``CPU_OFF`` on all non-lead CPUs in sequence then ``CPU_SUSPEND`` on lead CPU to deepest power level
434 2. Program wake up timer and suspend the lead CPU to the deepest power level.
456 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
459 lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
498 effects, given that these measurements are at the nano-second level.