Merge "fix(xlat): typecast expressions to match data type" into integration

fix(xlat): typecast expressions to match data type

This corrects the MISRA violation C2012-11.5:
type casting the void pointer expression with the object pointer type.

Change-Id: I9f4b648509662e6f6

fix(xlat): typecast expressions to match data type

This corrects the MISRA violation C2012-11.5:
type casting the void pointer expression with the object pointer type.

Change-Id: I9f4b648509662e6f6e676613f3cc3984815c9862
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes from topic "ffa_mem_perm_get_update" into integration

* changes:
feat(spm): update MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 interface
feat(el3-spmc): update FFA_MEM_PERM_GET interface

feat(el3-spmc): update FFA_MEM_PERM_GET interface

Update FFA_MEM_PERM_GET interface
according to FF-A v1.3 memory management protocol modification [0].
This adds one input/output parameter with page

feat(el3-spmc): update FFA_MEM_PERM_GET interface

Update FFA_MEM_PERM_GET interface
according to FF-A v1.3 memory management protocol modification [0].
This adds one input/output parameter with page_count
to set search range and get the range having the same
permission from base_va.

This change is backward compatible with former FF-A v1.2 interface.

Links: https://developer.arm.com/documentation/den0140/latest/
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I5c9679c9da1126b1df65f22a803776029ab52b12

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Merge "fix(xlat): correct attribute retrieval in a RME enabled system" into integration

fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm a

fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.

Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge "fix(xlat): fix bug on VERBOSE trace" into integration

fix(xlat): fix bug on VERBOSE trace

When log level is set to VERBOSE, a build error
happens due a incorrect format stringon a printf
call.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobri

fix(xlat): fix bug on VERBOSE trace

When log level is set to VERBOSE, a build error
happens due a incorrect format stringon a printf
call.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I8f869e078a3c179470977dadc063521c1ae30dbb

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Merge changes from topic "za/feat_rme" into integration

* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme

Merge changes from topic "za/feat_rme" into integration

* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme): add build and run instructions for FEAT_RME
fix(plat/fvp): bump BL2 stack size
fix(plat/fvp): allow changing the kernel DTB load address
refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
refactor(plat/fvp): update FVP platform DTS for FEAT_RME
feat(plat/arm): add GPT initialization code for Arm platforms
feat(plat/fvp): add memory map for FVP platform for FEAT_RME
refactor(plat/arm): modify memory region attributes to account for FEAT_RME
feat(plat/fvp): add RMM image support for FVP platform
feat(rme): add GPT Library
feat(rme): add ENABLE_RME build option and support for RMM image
refactor(makefile): remove BL prefixes in build macros
feat(rme): add context management changes for FEAT_RME
feat(rme): add Test Realm Payload (TRP)
feat(rme): add RMM dispatcher (RMMD)
feat(rme): run BL2 in root world when FEAT_RME is enabled
feat(rme): add xlat table library changes for FEAT_RME
feat(rme): add Realm security state definition
feat(rme): add register definitions and helper functions for FEAT_RME

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feat(rme): add xlat table library changes for FEAT_RME

FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation a

feat(rme): add xlat table library changes for FEAT_RME

FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation according to the following mapping:

TTD.NSE TTD.NS | PAS
=================================
0 0 | Secure
0 1 | Non-secure
1 0 | Root
1 1 | Realm

This patch adds modifications to version 2 of the translation table
library accordingly. Bits 4 and 5 in mmap attribute are used to
determine the PAS.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103

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Merge "Increase type widths to satisfy width requirements" into integration

Increase type widths to satisfy width requirements

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
T

Increase type widths to satisfy width requirements

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

92407e73 and x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge "xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config" into integration

xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did n

xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did not do the required
cache maintenance after the mmap tables are modified if
WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned
off during power down, the tables in memory are accessed as part of cache
maintenance for power down, and the tables are not correct at this point which
results in a data abort.
This patch removes the optimization within xlat_change_mem_attributes_ctx()
when WARMBOOT_ENABLE_DCACHE_EARLY is enabled.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87

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Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge "Add support for Branch Target Identification" into integration

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge pull request #1900 from soby-mathew/sm/revert_xlat_changes

xlat_tables_v2: Revert recent changes to remove recursion

xlat_tables_v2: Revert recent changes to remove recursion

This commit reverts the following commits:

- c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion")
- db8cac2d986a ("xlat_tab

xlat_tables_v2: Revert recent changes to remove recursion

This commit reverts the following commits:

- c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion")
- db8cac2d986a ("xlat_tables_v2: unmap region without recursion.")
- 0ffe269215bd ("xlat_tables_v2: map region without recursion.")

This was part of PR#1843.

A problem has been detected in one of our test run configurations
involving dynamic mapping of regions and it is blocking the next
release. Until the problem can be solved, it is safer to revert
the changes.

Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursion

Remove recursion from xlat_tables_v2 library

xlat_tables_v2: print xlat tables without recursion

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversa

xlat_tables_v2: print xlat tables without recursion

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase