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Searched refs:bits (Results 1 – 25 of 54) sorted by relevance

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/rk3399_ARM-atf/lib/zlib/
H A Dinffast.c65 unsigned bits; /* local strm->bits */ in inflate_fast() local
92 bits = state->bits; in inflate_fast()
101 if (bits < 15) { in inflate_fast()
102 hold += (unsigned long)(*in++) << bits; in inflate_fast()
103 bits += 8; in inflate_fast()
104 hold += (unsigned long)(*in++) << bits; in inflate_fast()
105 bits += 8; in inflate_fast()
109 op = (unsigned)(here->bits); in inflate_fast()
111 bits -= op; in inflate_fast()
123 if (bits < op) { in inflate_fast()
[all …]
H A Dinflate.c122 state->bits = 0; in inflateResetKeep()
223 int ZEXPORT inflatePrime(z_streamp strm, int bits, int value) { in inflatePrime() argument
227 if (bits == 0) in inflatePrime()
230 if (bits < 0) { in inflatePrime()
232 state->bits = 0; in inflatePrime()
235 if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR; in inflatePrime()
236 value &= (1L << bits) - 1; in inflatePrime()
237 state->hold += (unsigned)value << state->bits; in inflatePrime()
238 state->bits += (uInt)bits; in inflatePrime()
260 unsigned sym, bits; in fixedtables() local
[all …]
H A Dinftrees.c34 unsigned FAR *bits, unsigned short FAR *work) { in inflate_table() argument
108 root = *bits; in inflate_table()
114 here.bits = (unsigned char)1; in inflate_table()
118 *bits = 1; in inflate_table()
211 here.bits = (unsigned char)(len - drop); in inflate_table()
280 (*table)[low].bits = (unsigned char)root; in inflate_table()
290 here.bits = (unsigned char)(len - drop); in inflate_table()
297 *bits = root; in inflate_table()
H A Dinftrees.h26 unsigned char bits; /* bits in this part of the code */ member
62 unsigned FAR *bits, unsigned short FAR *work);
H A Dinflate.h103 unsigned bits; /* number of bits in hold */ member
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/
H A Dt194_nvg.h156 } bits; member
165 } bits; member
176 } bits; member
185 } bits; member
196 } bits; member
206 } bits; member
214 } bits; member
245 } bits; member
253 } bits; member
263 } bits; member
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/rk3399_ARM-atf/include/drivers/brcm/
H A Dchimp.h48 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
49 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
68 static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
71 static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.h89 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
90 (((bits) & (msk)) << (bits_shift))
91 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
93 REG_SET_BITS(bits, bits_shift, msk))
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c47 static void a3700_gicd_ctlr_clear_bits(uint32_t bits) in a3700_gicd_ctlr_clear_bits() argument
52 if ((val & bits) != 0U) { in a3700_gicd_ctlr_clear_bits()
53 a3700_gicd_write(GICD_CTLR, val & ~bits); in a3700_gicd_ctlr_clear_bits()
58 bits); in a3700_gicd_ctlr_clear_bits()
/rk3399_ARM-atf/plat/rockchip/common/include/
H A Dplat_private.h55 #define BITS_SHIFT(bits, shift) ((bits) << (shift)) argument
59 #define BITS_WITH_WMASK(bits, msk, shift)\ argument
60 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.h125 #define REG_SET_BITS(bits, bits_shift, msk) \ argument
126 (((bits) & (msk)) << (bits_shift))
127 #define REG_WMSK_BITS(bits, bits_shift, msk) \ argument
129 REG_SET_BITS(bits, bits_shift, msk))
/rk3399_ARM-atf/include/bl31/
H A Dehf.h34 #define EHF_REGISTER_PRIORITIES(priorities, num, bits) \ argument
38 .pri_bits = (bits), \
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-2.rst41 A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
H A Dsecurity-advisory-tfv-3.rst56 The vulnerability is due to incorrect handling of the execute-never bits in the
59 handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
68 of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
/rk3399_ARM-atf/drivers/brcm/
H A Dchimp.c49 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
52 mmio_clrbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_clrbits()
55 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
58 mmio_setbits_32(CHIMP_INDIRECT_TGT_ADDR(addr), bits); in bcm_chimp_setbits()
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h16 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) argument
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h12 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) argument
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h12 #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) argument
/rk3399_ARM-atf/drivers/nxp/ddr/fsl-mmdc/
H A Dfsl_mmdc.c24 unsigned int bits) in set_wait_for_bits_clear() argument
30 while ((ddr_in32(ptr) & bits) != 0) { in set_wait_for_bits_clear()
/rk3399_ARM-atf/fdts/
H A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi9 * DDR width: 32bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz"
H A Dstm32mp15-ddr3-1x4Gb-1066-binG.dtsi9 * DDR width: 16bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
H A Dstm32mp15-ddr3-1x2Gb-1066-binG.dtsi9 * DDR width: 16bits
18 #define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
/rk3399_ARM-atf/plat/intel/soc/common/lib/sha/
H A Dsha.c201 uint64_t *bits = (uint64_t *)(sctx->buf + bit_offset); in sha512_base_do_finalize() local
213 bits[0] = cpu_to_be64(sctx->count[1] << 3 | sctx->count[0] >> 61); in sha512_base_do_finalize()
214 bits[1] = cpu_to_be64(sctx->count[0] << 3); in sha512_base_do_finalize()
/rk3399_ARM-atf/docs/components/
H A Dffa-manifest-binding.rst25 - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
375 - A list of (id, mpdir upper bits, mpidr lower bits) tuples describing which
380 - mpidr upper bits: The <u32> describing the upper bits of the 64 bits
382 - mpidr lower bits: The <u32> describing the lower bits of the 64 bits
H A Dven-el3-debugfs.rst333 uint32_t w1: On success, debugfs interface version, 32 bits
334 value with major version number in upper 16 bits and
335 minor version in lower 16 bits.

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