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Searched refs:TIMER_CONTROL_REG (Results 1 – 16 of 16) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
100 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in sram_secure_timer_init()
112 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in secure_timer_init()
118 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
H A Dsecure.h86 #define TIMER_CONTROL_REG 0x10 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/secure/
H A Dsecure.c17 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
24 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/
H A Dsoc.c39 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS); in secure_timer_init()
44 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
H A Dsoc.h35 #define TIMER_CONTROL_REG 0x10 macro
/rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/
H A Dsecure.c52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
H A Dsecure.h50 #define TIMER_CONTROL_REG 0x10 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.c118 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in sram_secure_timer_init()
131 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
H A Dsecure.h84 #define TIMER_CONTROL_REG 0x1c macro
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/secure/
H A Dsecure.c135 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
142 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h15 #define TIMER_CONTROL_REG 0x10 macro
H A Dsoc.c95 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.h27 #define TIMER_CONTROL_REG 0x10 macro
H A Dsoc.c74 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h131 #define TIMER_CONTROL_REG 0x10 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h185 #define TIMER_CONTROL_REG 0x10 macro