1 /*
2 * Copyright (c) 2024-2026, Rockchip, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <lib/mmio.h>
9
10 #include <platform_def.h>
11
12 #include "secure.h"
13 #include <soc.h>
14
15 /* unit: Mb */
ddr_fw_rgn_config(uint64_t base_mb,uint64_t top_mb,int rgn_id)16 static void ddr_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id)
17 {
18 if (rgn_id >= FIREWALL_DDR_RGN_CNT || rgn_id < 0) {
19 ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id);
20 panic();
21 }
22
23 /*
24 * The firewall regions are managed in 128KB blocks instead of
25 * the 1MB blocks on the RK3576 and RK3588 SoCs.
26 */
27 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_RGN(rgn_id),
28 RG_MAP_SECURE(top_mb * 8, base_mb * 8));
29
30 /* enable region */
31 mmio_setbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON, BIT(rgn_id));
32 }
33
secure_region_init(void)34 static void secure_region_init(void)
35 {
36 /* disable all region first except region0 */
37 mmio_clrbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON, 0xfffe);
38
39 /* Use FW_DDR_RGN0_REG to config 0~1M space to secure */
40 ddr_fw_rgn_config(0, 1, 0);
41 }
42
secure_timer_init(void)43 void secure_timer_init(void)
44 {
45 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS);
46 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
47 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
48
49 /* auto reload & enable the timer */
50 mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
51 }
52
sgrf_init(void)53 void sgrf_init(void)
54 {
55 secure_region_init();
56
57 /* config all slave as ns for now */
58 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000);
59 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000);
60 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000);
61 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000);
62 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000);
63 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000);
64 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000);
65 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000);
66 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000);
67 }
68