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Searched refs:SRAM_BASE (Results 1 – 14 of 14) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3288/include/
H A Dplat_sp_min.ld.S12 SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
18 . = SRAM_BASE;
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dhikey_def.h36 #define SRAM_BASE 0xFFF80000 macro
80 #define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
/rk3399_ARM-atf/plat/rockchip/rk3399/include/
H A Dplat.ld.S12 SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
18 . = SRAM_BASE;
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl1_setup.c85 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && in bl1_platform_setup()
86 ((SRAM_BASE + SRAM_SIZE) >= in bl1_platform_setup()
H A Dhikey_bl2_setup.c300 memset((void *)SRAM_BASE, 0, SRAM_SIZE); in bl2_platform_setup()
315 clean_dcache_range(SRAM_BASE, SRAM_SIZE); in bl2_platform_setup()
/rk3399_ARM-atf/plat/arm/board/a5ds/include/
H A Dplatform_def.h25 #define SRAM_BASE 0x2000000 macro
29 #define A5DS_SHARED_RAM_BASE SRAM_BASE
125 SRAM_BASE, \
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h59 #define SRAM_BASE 0xff000000 macro
144 #define SRAM_ENTRY_BASE SRAM_BASE
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c218 mmio_write_32(SRAM_BASE + 8, cpu_warm_boot_addr); in rockchip_soc_cores_pwr_dm_on()
219 mmio_write_32(SRAM_BASE + 4, 0xDEADBEAF); in rockchip_soc_cores_pwr_dm_on()
/rk3399_ARM-atf/plat/rockchip/rk3288/
H A Drk3288_def.h47 #define SRAM_BASE 0xff700000 macro
/rk3399_ARM-atf/plat/hisilicon/hikey/aarch64/
H A Dhikey_common.c35 #define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h47 #define SRAM_BASE (MMIO_BASE + 0x078C0000) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h138 #define SRAM_BASE 0x3ff80000 macro
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c33 MAP_REGION_FLAT(SRAM_BASE, SRAM_SIZE,
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c799 mmio_write_32(SRAM_BASE + 0x08, (uintptr_t)&cpus_pd_req_enter_wfi); in nonboot_cpus_off()
800 mmio_write_32(SRAM_BASE + 0x04, 0xdeadbeaf); in nonboot_cpus_off()