1*780e3f24SHeiko Stuebner/* 2*780e3f24SHeiko Stuebner * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*780e3f24SHeiko Stuebner * 4*780e3f24SHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5*780e3f24SHeiko Stuebner */ 6*780e3f24SHeiko Stuebner#ifndef ROCKCHIP_PLAT_LD_S 7*780e3f24SHeiko Stuebner#define ROCKCHIP_PLAT_LD_S 8*780e3f24SHeiko Stuebner 9*780e3f24SHeiko Stuebner#include <lib/xlat_tables/xlat_tables_defs.h> 10*780e3f24SHeiko Stuebner 11*780e3f24SHeiko StuebnerMEMORY { 12*780e3f24SHeiko Stuebner SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 13*780e3f24SHeiko Stuebner PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 14*780e3f24SHeiko Stuebner} 15*780e3f24SHeiko Stuebner 16*780e3f24SHeiko StuebnerSECTIONS 17*780e3f24SHeiko Stuebner{ 18*780e3f24SHeiko Stuebner . = SRAM_BASE; 19*780e3f24SHeiko Stuebner ASSERT(. == ALIGN(PAGE_SIZE), 20*780e3f24SHeiko Stuebner "SRAM_BASE address is not aligned on a page boundary.") 21*780e3f24SHeiko Stuebner 22*780e3f24SHeiko Stuebner .text_sram : ALIGN(PAGE_SIZE) { 23*780e3f24SHeiko Stuebner __bl32_sram_text_start = .; 24*780e3f24SHeiko Stuebner *(.sram.text) 25*780e3f24SHeiko Stuebner *(.sram.rodata) 26*780e3f24SHeiko Stuebner __bl32_sram_text_real_end = .; 27*780e3f24SHeiko Stuebner . = ALIGN(PAGE_SIZE); 28*780e3f24SHeiko Stuebner __bl32_sram_text_end = .; 29*780e3f24SHeiko Stuebner } >SRAM 30*780e3f24SHeiko Stuebner ASSERT((__bl32_sram_text_real_end - __bl32_sram_text_start) <= 31*780e3f24SHeiko Stuebner SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit") 32*780e3f24SHeiko Stuebner 33*780e3f24SHeiko Stuebner .data_sram : ALIGN(PAGE_SIZE) { 34*780e3f24SHeiko Stuebner __bl32_sram_data_start = .; 35*780e3f24SHeiko Stuebner *(.sram.data) 36*780e3f24SHeiko Stuebner __bl32_sram_data_real_end = .; 37*780e3f24SHeiko Stuebner . = ALIGN(PAGE_SIZE); 38*780e3f24SHeiko Stuebner __bl32_sram_data_end = .; 39*780e3f24SHeiko Stuebner } >SRAM 40*780e3f24SHeiko Stuebner ASSERT((__bl32_sram_data_real_end - __bl32_sram_data_start) <= 41*780e3f24SHeiko Stuebner SRAM_DATA_LIMIT, ".data_sram has exceeded its limit") 42*780e3f24SHeiko Stuebner 43*780e3f24SHeiko Stuebner .stack_sram : ALIGN(PAGE_SIZE) { 44*780e3f24SHeiko Stuebner __bl32_sram_stack_start = .; 45*780e3f24SHeiko Stuebner . += PAGE_SIZE; 46*780e3f24SHeiko Stuebner __bl32_sram_stack_end = .; 47*780e3f24SHeiko Stuebner } >SRAM 48*780e3f24SHeiko Stuebner 49*780e3f24SHeiko Stuebner . = PMUSRAM_BASE; 50*780e3f24SHeiko Stuebner 51*780e3f24SHeiko Stuebner /* 52*780e3f24SHeiko Stuebner * pmu_cpuson_entrypoint request address 53*780e3f24SHeiko Stuebner * align 64K when resume, so put it in the 54*780e3f24SHeiko Stuebner * start of pmusram 55*780e3f24SHeiko Stuebner */ 56*780e3f24SHeiko Stuebner .pmusram : { 57*780e3f24SHeiko Stuebner ASSERT(. == ALIGN(64 * 1024), 58*780e3f24SHeiko Stuebner ".pmusram.entry request 64K aligned."); 59*780e3f24SHeiko Stuebner *(.pmusram.entry) 60*780e3f24SHeiko Stuebner 61*780e3f24SHeiko Stuebner __bl32_pmusram_text_start = .; 62*780e3f24SHeiko Stuebner *(.pmusram.text) 63*780e3f24SHeiko Stuebner *(.pmusram.rodata) 64*780e3f24SHeiko Stuebner __bl32_pmusram_text_end = .; 65*780e3f24SHeiko Stuebner 66*780e3f24SHeiko Stuebner __bl32_pmusram_data_start = .; 67*780e3f24SHeiko Stuebner *(.pmusram.data) 68*780e3f24SHeiko Stuebner __bl32_pmusram_data_end = .; 69*780e3f24SHeiko Stuebner } >PMUSRAM 70*780e3f24SHeiko Stuebner} 71*780e3f24SHeiko Stuebner 72*780e3f24SHeiko Stuebner#endif /* ROCKCHIP_PLAT_LD_S */ 73