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Searched refs:SOCFPGA_LWSOC2FPGA_SCR_REG_BASE (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h53 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h52 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h69 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h86 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c115 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, in bl2_el3_early_platform_setup()
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_firewall.c129 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL); in enable_ns_bridge_access()