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Searched refs:SOCFPGA_L4_SYS_SCR_REG_BASE (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h51 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h50 #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) macro
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_noc.h24 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h67 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h84 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c113 mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT, in bl2_el3_early_platform_setup()