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Searched refs:SGRF_BASE (Results 1 – 23 of 23) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.c21 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
74 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), in sgrf_ddr_rgn_config()
81 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_config()
92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_gate()
104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_ungate()
138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), in secure_sgrf_init()
140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), in secure_sgrf_init()
142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), in secure_sgrf_init()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), in sgrf_ddr_rgn_config()
74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); in secure_watchdog_gate()
89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); in secure_watchdog_ungate()
132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), SGRF_SOC_CON2_MST_NS); in secure_sgrf_init()
133 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_SOC_CON3_MST_NS); in secure_sgrf_init()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/
H A Dsecure.c84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); in sgrf_init()
85 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); in sgrf_init()
86 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); in sgrf_init()
87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); in sgrf_init()
88 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); in sgrf_init()
91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); in sgrf_init()
94 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); in sgrf_init()
95 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); in sgrf_init()
96 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); in sgrf_init()
97 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); in sgrf_init()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/
H A Dsoc.c49 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000); in sgrf_init()
50 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000); in sgrf_init()
51 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000); in sgrf_init()
52 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000); in sgrf_init()
53 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000); in sgrf_init()
54 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000); in sgrf_init()
55 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000); in sgrf_init()
56 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000); in sgrf_init()
57 mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000); in sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dm0_ctl.c23 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); in m0_init()
24 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); in m0_init()
46 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), in m0_configure_execute_addr()
49 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), in m0_configure_execute_addr()
H A Dpmu.c1378 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_suspend()
1459 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_resume()
1609 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in plat_rockchip_pmu_init()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.c30 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000); in sgrf_init()
136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS); in sgrf_init()
137 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS); in sgrf_init()
140 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS); in sgrf_init()
141 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0); in sgrf_init()
142 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16); in sgrf_init()
143 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS); in sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c234 mmio_write_32(SGRF_BASE + SGRF_CPU_CON(0), in rockchip_soc_sys_pwr_dm_resume()
238 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), in rockchip_soc_sys_pwr_dm_resume()
256 store_sgrf_cpu_con0 = mmio_read_32(SGRF_BASE + SGRF_CPU_CON(0)); in rockchip_soc_sys_pwr_dm_suspend()
257 store_sgrf_soc_con0 = mmio_read_32(SGRF_BASE + SGRF_SOC_CON(0)); in rockchip_soc_sys_pwr_dm_suspend()
275 mmio_write_32(SGRF_BASE + SGRF_CPU_CON(0), SGRF_DAPDEVICE_MSK); in rockchip_soc_sys_pwr_dm_suspend()
280 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_FAST_BOOT_ENA); in rockchip_soc_sys_pwr_dm_suspend()
283 mmio_write_32(SGRF_BASE + SGRF_FAST_BOOT_ADDR, in rockchip_soc_sys_pwr_dm_suspend()
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.c27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); in sgrf_init()
81 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); in sgrf_init()
82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); in sgrf_init()
85 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); in sgrf_init()
86 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); in sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/pmu/
H A Dpmu.c232 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in pmu_set_sleep_mode()
235 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), in pmu_set_sleep_mode()
314 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
321 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
335 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_resume()
338 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), in rockchip_soc_sys_pwr_dm_resume()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/
H A Dotp.c168 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2, in otp_select()
173 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2, in otp_select()
223 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2, in rk_otp_sbpi_read()
307 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2, in rk_otp_sbpi_read()
/rk3399_ARM-atf/plat/rockchip/rk3368/
H A Drk3368_def.h28 #define SGRF_BASE 0xff740000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h40 #define SGRF_BASE 0xfdd18000 macro
/rk3399_ARM-atf/plat/rockchip/rk3288/
H A Drk3288_def.h57 #define SGRF_BASE 0xff740000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram.c22 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> in dram_init()
H A Dsuspend.c119 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in configure_sgrf()
/rk3399_ARM-atf/plat/rockchip/rk3328/
H A Drk3328_def.h30 #define SGRF_BASE 0xff0d0000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h97 #define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
H A Daddressmap_shared.h28 #define SGRF_BASE (MMIO_BASE + 0x07330000) macro
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h43 #define SGRF_BASE 0xff11c000 macro
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c602 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in sram_suspend()
656 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in plat_rockchip_pmu_init()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c537 mmio_write_32(SGRF_BASE + 0x008, 0x00100000); in plat_rockchip_pmu_init()