| /rk3399_ARM-atf/plat/imx/imx8m/ |
| H A D | imx8m_psci_common.c | 95 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_cpu_standby()
100 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_cpu_standby()
116 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_domain_suspend()
150 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/common/ |
| H A D | plat_gicv3.c | 175 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()
184 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()
194 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()
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| H A D | plat_gicv2.c | 159 return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : in plat_interrupt_type_to_line()
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| /rk3399_ARM-atf/plat/imx/imx8qx/ |
| H A D | imx8qx_psci.c | 123 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_domain_suspend()
211 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mq/ |
| H A D | imx8mq_psci.c | 72 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_domain_suspend()
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| /rk3399_ARM-atf/plat/rpi/common/ |
| H A D | rpi3_common.c | 230 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()
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| /rk3399_ARM-atf/plat/imx/imx8qm/ |
| H A D | imx8qm_psci.c | 149 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_domain_suspend()
278 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | imx8ulp_psci.c | 318 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in imx_domain_suspend()
429 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()
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| /rk3399_ARM-atf/drivers/renesas/common/watchdog/ |
| H A D | swdt.c | 145 write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT); in rcar_swdt_release()
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| /rk3399_ARM-atf/plat/arm/css/common/ |
| H A D | css_pm.c | 237 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in css_cpu_standby()
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| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_pm.c | 129 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in fvp_cpu_standby()
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| /rk3399_ARM-atf/plat/brcm/board/stingray/src/ |
| H A D | brcm_pm_ops.c | 207 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in brcm_cpu_standby()
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| /rk3399_ARM-atf/plat/nuvoton/npcm845x/ |
| H A D | npcm845x_psci.c | 106 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in npcm845x_cpu_standby()
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| /rk3399_ARM-atf/include/services/ |
| H A D | arm_arch_svc.h | 232 SCR_FIQ_BIT | \
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_pm.c | 47 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in hikey960_pwr_domain_standby()
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| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_psci.c | 32 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in k3_cpu_standby()
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| /rk3399_ARM-atf/bl32/sp_min/aarch32/ |
| H A D | entrypoint.S | 35 orr \reg, \reg, #SCR_FIQ_BIT
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| /rk3399_ARM-atf/plat/mediatek/mt8195/ |
| H A D | plat_pm.c | 184 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/ |
| H A D | plat_pm.c | 186 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
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| /rk3399_ARM-atf/plat/mediatek/mt8186/ |
| H A D | plat_pm.c | 179 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
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| /rk3399_ARM-atf/plat/mediatek/mt8183/ |
| H A D | plat_pm.c | 203 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); in plat_cpu_standby()
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | 712 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
760 #define SCR_FIQ_BIT (UL(1) << 2) macro
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| /rk3399_ARM-atf/plat/renesas/rzg/ |
| H A D | bl2_plat_setup.c | 706 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in bl2_el3_early_platform_setup()
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch.h | 242 #define SCR_FIQ_BIT (UL(1) << 2) macro
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| /rk3399_ARM-atf/plat/renesas/rcar/ |
| H A D | bl2_plat_setup.c | 1075 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); in bl2_el3_early_platform_setup()
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