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Searched refs:PLAT_TIMER_BASE_ADDR (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_delay_timer.c22 #define SOCFPGA_GLOBAL_TIMER PLAT_TIMER_BASE_ADDR
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Dsocfpga_plat_def.h21 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 macro
/rk3399_ARM-atf/plat/intel/soc/n5x/include/
H A Dsocfpga_plat_def.h22 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dsocfpga_plat_def.h27 #define PLAT_TIMER_BASE_ADDR 0xFFD01000 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h31 #define PLAT_TIMER_BASE_ADDR 0x10D01000 macro