Searched refs:NS_DRAM0_BASE (Results 1 – 8 of 8) sorted by relevance
82 #define NS_DRAM0_BASE ULL(0x00400000) macro100 #define NS_DRAM0_BASE ULL(0x11000000) macro105 #define FW_NS_HANDOFF_BASE NS_DRAM0_BASE110 #define PLAT_RPI3_NS_IMAGE_OFFSET NS_DRAM0_BASE + FW_HANDOFF_SIZE
83 #define NS_DRAM0_BASE ULL(0x40000000) macro 192 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000)287 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE358 #define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE)
67 #define QEMU_PAS_NS0_BASE NS_DRAM0_BASE
83 #define NS_DRAM0_BASE (PLAT_QEMU_DRAM0_BASE + \ macro 203 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000)310 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
49 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \239 bank_ptr->base = NS_DRAM0_BASE; in plat_get_memory_node()
37 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
417 if (set_system_memory_base(dtb, NS_DRAM0_BASE)) { in sbsa_platform_init()
1620 …- dissociate QEMU NS start address and NS_DRAM0_BASE ([26da60e](https://review.trustedfirmware.org…9250 …- (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit ([325716c](https://review.trustedfirmware.or…