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Searched refs:MHZ (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_modules.c10 #define S32CC_A53_MIN_FREQ (48UL * MHZ)
11 #define S32CC_A53_MAX_FREQ (1000UL * MHZ)
23 S32CC_OSC_INIT_FREQ(S32CC_FIRC, 48 * MHZ);
42 S32CC_FREQ_MODULE_CLK(armpll, 1400 * MHZ, 2000 * MHZ);
55 S32CC_FREQ_MODULE_CLK(arm_dfs1_div, 0, 800 * MHZ);
79 S32CC_CHILD_CLK(cgm0_mux0_clk, 48 * MHZ, 800 * MHZ);
83 S32CC_FREQ_MODULE_CLK(xbar_div2, 24 * MHZ, 400 * MHZ);
87 S32CC_FREQ_MODULE_CLK(xbar_div4, 12 * MHZ, 200 * MHZ);
91 S32CC_FREQ_MODULE_CLK(xbar_div6, 8 * MHZ, 133333333);
95 S32CC_FREQ_MODULE_CLK(xbar_div8, 6 * MHZ, 100 * MHZ);
[all …]
H A Ds32cc_early_clks.c14 #define S32CC_FXOSC_FREQ (40U * MHZ)
18 #define S32CC_XBAR_2X_FREQ (800U * MHZ)
21 #define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
22 #define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
23 #define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ)
24 #define S32CC_USDHC_FREQ (200U * MHZ)
H A Ds32cc_clk_drv.c491 sclk_freq = 48U * MHZ; in enable_pll()
495 sclk_freq = 40U * MHZ; in enable_pll()
/rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/
H A Ds32cc-clk-modules.h12 #define MHZ UL(1000000) macro
13 #define GHZ (UL(1000) * MHZ)
/rk3399_ARM-atf/docs/plat/
H A Drcar-gen3.rst60 HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S)
61 QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI