Searched refs:IMX_DDRC_BASE (Results 1 – 5 of 5) sorted by relevance
26 #define IMX_DDRC_BASE U(0x2E060000) macro167 mmio_write_32(IMX_DDRC_BASE + i * 4, dram_timing_cfg->ctl_cfg[i]); in ddr_init()172 mmio_write_32(IMX_DDRC_BASE + 0x2000 + i * 4, dram_timing_cfg->pi_cfg[i]); in ddr_init()177 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x100); in ddr_init()199 mmio_write_32(IMX_DDRC_BASE + 0x4000 + i * 4, dram_timing_cfg->phy_full[i]); in ddr_init()204 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x0); in ddr_init()206 mmio_write_32(IMX_DDRC_BASE + 0x4000 + freq_specific_reg_array[i] * 4, in ddr_init()212 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, PHY_FREQ_MULTICAST_EN(1)); in ddr_init()221 lp_auto_en = (mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & (LP_AUTO_ENTRY_EN << 24)); in dram_lp_auto_disable()223 dram_ctl_143 = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_143); in dram_lp_auto_disable()[all …]
96 #define IMX_DDRC_BASE U(0x3d400000) macro
116 #define IMX_DDRC_BASE U(0x3d400000) macro
99 #define IMX_DDRC_BASE U(0x3d400000) macro
119 #define IMX_DDRC_BASE U(0x3d400000) macro