Lines Matching refs:IMX_DDRC_BASE
26 #define IMX_DDRC_BASE U(0x2E060000) macro
167 mmio_write_32(IMX_DDRC_BASE + i * 4, dram_timing_cfg->ctl_cfg[i]); in ddr_init()
172 mmio_write_32(IMX_DDRC_BASE + 0x2000 + i * 4, dram_timing_cfg->pi_cfg[i]); in ddr_init()
177 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x100); in ddr_init()
199 mmio_write_32(IMX_DDRC_BASE + 0x4000 + i * 4, dram_timing_cfg->phy_full[i]); in ddr_init()
204 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x0); in ddr_init()
206 mmio_write_32(IMX_DDRC_BASE + 0x4000 + freq_specific_reg_array[i] * 4, in ddr_init()
212 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, PHY_FREQ_MULTICAST_EN(1)); in ddr_init()
221 lp_auto_en = (mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & (LP_AUTO_ENTRY_EN << 24)); in dram_lp_auto_disable()
223 dram_ctl_143 = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_143); in dram_lp_auto_disable()
227 dram_timing_cfg->auto_lp_cfg[0] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_144); in dram_lp_auto_disable()
228 dram_timing_cfg->auto_lp_cfg[1] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_147); in dram_lp_auto_disable()
229 dram_timing_cfg->auto_lp_cfg[2] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146); in dram_lp_auto_disable()
231 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_143, 0xF << 24); in dram_lp_auto_disable()
233 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_CTL_146, LP_AUTO_ENTRY_EN << 24); in dram_lp_auto_disable()
237 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & in dram_lp_auto_disable()
242 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_CTL_147, LP_AUTO_EXIT_EN); in dram_lp_auto_disable()
253 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & in dram_lp_auto_enable()
266 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, dram_timing_cfg->auto_lp_cfg[0]); in dram_lp_auto_enable()
267 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_147, dram_timing_cfg->auto_lp_cfg[1]); in dram_lp_auto_enable()
269 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_146, dram_timing_cfg->auto_lp_cfg[2]); in dram_lp_auto_enable()
271 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_143, dram_ctl_143); in dram_lp_auto_enable()
292 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_self_refresh()
333 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_retention()
358 dram_class = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_00); in dram_enter_retention()
363 dram_timing_cfg->ctl_cfg[i] = mmio_read_32(IMX_DDRC_BASE + i * 4); in dram_enter_retention()
369 dram_timing_cfg->pi_cfg[i] = mmio_read_32(IMX_DDRC_BASE + 0x2000 + i * 4); in dram_enter_retention()
378 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x10000); in dram_enter_retention()
384 dram_timing_cfg->phy_full[i] = mmio_read_32(IMX_DDRC_BASE + 0x4000 + i * 4); in dram_enter_retention()
392 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1537, 0x0); in dram_enter_retention()
395 dram_timing_cfg->phy_diff[i] = mmio_read_32(IMX_DDRC_BASE + 0x4000 + in dram_enter_retention()
424 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1559, 0x01010101); in dram_exit_retention()
442 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_137, 0x1); in dram_exit_retention()
444 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_132, 0x01000000); in dram_exit_retention()
446 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_PI_132, BIT(16)); in dram_exit_retention()
448 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_PI_04, BIT(0)); in dram_exit_retention()
450 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_174, 0x03030000); in dram_exit_retention()
452 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_175, 0x03); in dram_exit_retention()
454 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_191, 0x03030000); in dram_exit_retention()
456 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_192, 0x03); in dram_exit_retention()
458 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_212, 0x300); in dram_exit_retention()
460 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_214, 0x03000000); in dram_exit_retention()
462 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_217, 0x300); in dram_exit_retention()
464 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_181, 0x03030000); in dram_exit_retention()
469 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_182, 0x03030303); in dram_exit_retention()
471 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_134, 0x000F0000); in dram_exit_retention()
474 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_137, 0x1); in dram_exit_retention()
476 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_132, 0x01000000); in dram_exit_retention()
478 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_PI_132, BIT(16)); in dram_exit_retention()
480 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_PI_04, BIT(0)); in dram_exit_retention()
482 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_174, 0x00030000); in dram_exit_retention()
484 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_191, 0x00030000); in dram_exit_retention()
486 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_181, 0x03030000); in dram_exit_retention()
488 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_134, 0x000F0000); in dram_exit_retention()
491 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, 0x00002D00); in dram_exit_retention()
494 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, 0x1); in dram_exit_retention()
500 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_249, 0x0); in dram_exit_retention()
503 mmio_write_32(IMX_DDRC_BASE + DENALI_PHY_1590, 0x01000000); in dram_exit_retention()
505 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_25, 0x00020100); in dram_exit_retention()
508 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_153, 0x04040000); in dram_exit_retention()
519 mmio_write_32(IMX_DDRC_BASE + DENALI_PI_00, 0x00000b01); in dram_exit_retention()
522 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_00, 0x00000b01); in dram_exit_retention()
525 mmio_write_32(IMX_DDRC_BASE + DENALI_PI_00, 0x00000701); in dram_exit_retention()
528 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_00, 0x00000701); in dram_exit_retention()
533 val = (mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_266) >> 8) & 0xFF; in dram_exit_retention()
541 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_52, 0x10000); /* CALVL */ in dram_exit_retention()
542 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_26, 0x100); /* WRLVL */ in dram_exit_retention()
543 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x10000); /* RDGATE */ in dram_exit_retention()
544 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x100); /* RDQLVL */ in dram_exit_retention()
545 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_65, 0x10000); /* WDQLVL */ in dram_exit_retention()
548 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_PI_77) & 0x07E00000) != 0x07E00000) { in dram_exit_retention()
552 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_52, 0x10000); /* CALVL */ in dram_exit_retention()
553 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_26, 0x100); /* WRLVL */ in dram_exit_retention()
554 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x10000); /* RDGATE */ in dram_exit_retention()
555 mmio_setbits_32(IMX_DDRC_BASE + DENALI_PI_33, 0x100); /* RDQLVL */ in dram_exit_retention()
556 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_PI_77) & 0x05E00000) != 0x05E00000) { in dram_exit_retention()
649 ddr_ctl_144 = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_144); in lpddr4_dfs()
650 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, LPI_WAKEUP_EN); in lpddr4_dfs()
686 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, ddr_ctl_144); in lpddr4_dfs()