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Searched refs:DRAM_PLL_CTRL (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dclock.c87 mmio_setbits_32(DRAM_PLL_CTRL, (1 << 16)); in dram_pll_init()
88 mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); in dram_pll_init()
92 mmio_write_32(DRAM_PLL_CTRL + 0x4, (250 << 12) | (3 << 4) | 1); in dram_pll_init()
97 mmio_write_32(DRAM_PLL_CTRL + 0x4, (311 << 12) | (4 << 4) | 1); in dram_pll_init()
100 mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (8 << 4) | 0); in dram_pll_init()
103 mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (9 << 4) | 0); in dram_pll_init()
106 mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2); in dram_pll_init()
109 mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3); in dram_pll_init()
112 mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3); in dram_pll_init()
115 mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4); in dram_pll_init()
[all …]
H A Ddram_retention.c146 while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { in dram_exit_retention()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/
H A Dplatform_def.h147 #define DRAM_PLL_CTRL HW_DRAM_PLL_CFG0 macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/
H A Dplatform_def.h166 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/
H A Dplatform_def.h140 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/
H A Dplatform_def.h176 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) macro