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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/
H A Ds32cc-clk-regs.h109 #define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT(CSS) \ argument
111 & (CSS)) \
/rk3399_ARM-atf/docs/plat/arm/automotive_rd/
H A Drdaspen.rst1 RD-Aspen (Zena CSS) Platform
13 Further information on RD-Aspen is available at `Zena CSS`_
114 .. _Zena CSS: https://www.arm.com/products/automotive/compute-subsystems/zena
/rk3399_ARM-atf/docs/
H A Dglobal_substitutions.txt10 .. |CSS| replace:: :term:`CSS`
H A Dglossary.rst36 CSS
H A Dchange-log.md724 - **CSS**
1988 - **CSS**
2947 …- adapt order of CSS on LSE and HSE ([eca5103](https://review.trustedfirmware.org/plugins/gitiles/…
3085 …- add CSS definitions for third gen platforms ([6d52713](https://review.trustedfirmware.org/plugin…
3687 - **CSS**
5611 - **CSS**
6581 - **CSS**
H A Dporting-guide.rst2102 On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
/rk3399_ARM-atf/docs/design/
H A Dinterrupt-framework-design.rst90 #. **CSS**. Current Security State. ``0`` when secure and ``1`` when non-secure
98 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
102 #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
106 #. **CSS=1, TEL3=0**. Interrupt is routed to the FEL when execution is in
111 #. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
118 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
125 #. **CSS=0, TEL3=1**. Interrupt is routed to EL3 when execution is in secure
132 #. **CSS=1, TEL3=0**. Interrupt is routed to FEL when execution is in
136 #. **CSS=1, TEL3=1**. Interrupt is routed to EL3 when execution is in
146 #. **CSS=0, TEL3=0**. Interrupt is routed to the FEL when execution is in
[all …]
/rk3399_ARM-atf/fdts/
H A Dstmm_template.dts39 * ARM CSS SoC Peripherals area.
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/fdts/
H A Drdn2_stmm_sel0_manifest.dts64 * ARM CSS SoC Expansion Peripherals.
/rk3399_ARM-atf/docs/plat/arm/
H A Darm-build-options.rst119 Arm CSS Platform-Specific Build Options
138 CPU core on reset. This build option can be used on CSS platforms that
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h327 #define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ macro
H A Dclk-stm32mp13.c1655 CSS(RCC_BDCR, 8),
1660 CSS(RCC_OCENSETR, 11),
H A Dclk-stm32mp2.c659 CSS(RCC_OCENSETR, 11),
664 CSS(RCC_BDCR, 8),
/rk3399_ARM-atf/docs/components/
H A Dfirmware-update.rst159 Arm CSS platforms like Juno have a System Control Processor (SCP), and these
H A Dexception-handling.rst151 as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.