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Searched refs:CASSERT (Results 1 – 25 of 96) sorted by relevance

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/rk3399_ARM-atf/include/services/
H A Drmm_core_manifest.h55 CASSERT(offsetof(struct memory_bank, base) == 0UL,
57 CASSERT(offsetof(struct memory_bank, size) == 8UL,
67 CASSERT(offsetof(struct memory_info, num_banks) == 0UL,
69 CASSERT(offsetof(struct memory_info, banks) == 8UL,
71 CASSERT(offsetof(struct memory_info, checksum) == 16UL,
84 CASSERT(offsetof(struct console_info, base) == 0UL,
86 CASSERT(offsetof(struct console_info, map_pages) == 8UL,
88 CASSERT(offsetof(struct console_info, name) == 16UL,
90 CASSERT(offsetof(struct console_info, clk_in_hz) == 24UL,
92 CASSERT(offsetof(struct console_info, baud_rate) == 32UL,
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H A Drmm_el3_token_sign.h35 CASSERT(__builtin_offsetof(struct el3_token_sign_request, sig_alg_id) == 0x0U,
37 CASSERT(__builtin_offsetof(struct el3_token_sign_request, rec_granule) == 0x8U,
39 CASSERT(__builtin_offsetof(struct el3_token_sign_request, req_ticket) == 0x10U,
41 CASSERT(__builtin_offsetof(struct el3_token_sign_request, hash_alg_id) == 0x18U,
43 CASSERT(__builtin_offsetof(struct el3_token_sign_request, hash_buf) == 0x20U,
54 CASSERT(__builtin_offsetof(struct el3_token_sign_response, rec_granule) == 0x0U,
56 CASSERT(__builtin_offsetof(struct el3_token_sign_response, req_ticket) == 0x8U,
58 CASSERT(__builtin_offsetof(struct el3_token_sign_response, sig_len) == 0x10U,
60 CASSERT(__builtin_offsetof(struct el3_token_sign_response, signature_buf) == 0x12U,
H A Del3_spmc_ffa_memory.h39 CASSERT(sizeof(struct ffa_cons_mrd) == 16, assert_ffa_cons_mrd_size_mismatch);
60 CASSERT(sizeof(struct ffa_comp_mrd) == 16, assert_ffa_comp_mrd_size_mismatch);
171 CASSERT(sizeof(struct ffa_mapd) == 4, assert_ffa_mapd_size_mismatch);
186 CASSERT(sizeof(struct ffa_emad_v1_0) == 16, assert_ffa_emad_v1_0_size_mismatch);
219 CASSERT(sizeof(struct ffa_mtd_v1_0) == 32, assert_ffa_mtd_size_v1_0_mismatch);
220 CASSERT(offsetof(struct ffa_mtd_v1_0, emad) == 32,
258 CASSERT(sizeof(struct ffa_mtd) == 48, assert_ffa_mtd_size_mismatch);
259 CASSERT(offsetof(struct ffa_mtd, emad_count) ==
H A Darm_arch_svc.h239 CASSERT((SCR_EL3_FEATS & SCR_EL3_IGNORED) == 0, scr_feat_is_ignored);
240 CASSERT((SCR_EL3_FLIPPED & SCR_EL3_FEATS) == SCR_EL3_FLIPPED, scr_flipped_not_a_feat);
278 CASSERT((CPTR_EL3_FLIPPED & CPTR_EL3_FEATS) == CPTR_EL3_FLIPPED, cptr_flipped_not_a_feat);
363 CASSERT((MDCR_EL3_FEATS & MDCR_EL3_IGNORED) == 0, mdcr_feat_is_ignored);
364 CASSERT((MDCR_EL3_FLIPPED & MDCR_EL3_FEATS) == MDCR_EL3_FLIPPED, mdcr_flipped_not_a_feat);
369 CASSERT((MPAM3_EL3_FEATS & MPAM3_EL3_IGNORED) == 0, mpam3_feat_is_ignored);
370 CASSERT((MPAM3_EL3_FLIPPED & MPAM3_EL3_FEATS) == MPAM3_EL3_FLIPPED, mpam3_flipped_not_a_feat);
/rk3399_ARM-atf/include/drivers/
H A Dconsole_assertions.h16 CASSERT(CONSOLE_T_NEXT == __builtin_offsetof(console_t, next),
18 CASSERT(CONSOLE_T_FLAGS == __builtin_offsetof(console_t, flags),
20 CASSERT(CONSOLE_T_PUTC == __builtin_offsetof(console_t, putc),
23 CASSERT(CONSOLE_T_GETC == __builtin_offsetof(console_t, getc),
26 CASSERT(CONSOLE_T_FLUSH == __builtin_offsetof(console_t, flush),
28 CASSERT(CONSOLE_T_DRVDATA == sizeof(console_t),
/rk3399_ARM-atf/plat/rockchip/common/pmusram/
H A Dcpus_on_fixed_addr.h40 CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP,
42 CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC,
44 CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA,
46 CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
48 CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
/rk3399_ARM-atf/include/lib/el3_runtime/
H A Dsimd_ctx.h72 CASSERT(CTX_SIMD_VECTORS == __builtin_offsetof(simd_regs_t, vectors),
75 CASSERT(CTX_SIMD_FPSR == __builtin_offsetof(simd_regs_t, fpsr),
78 CASSERT(CTX_SIMD_FPCR == __builtin_offsetof(simd_regs_t, fpcr),
82 CASSERT(CTX_SIMD_FPEXC32 == __builtin_offsetof(simd_regs_t, fpexc32_el2),
87 CASSERT(CTX_SIMD_PREDICATES == __builtin_offsetof(simd_regs_t, predicates),
90 CASSERT(CTX_SIMD_FFR == __builtin_offsetof(simd_regs_t, ffr),
/rk3399_ARM-atf/include/drivers/arm/css/
H A Dcss_scp.h45 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
46 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
49 CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
50 CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
/rk3399_ARM-atf/include/arch/aarch32/
H A Dsmccc_helpers.h93 CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0),
95 CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1),
97 CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2),
99 CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3),
101 CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4),
103 CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr),
105 CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon),
107 CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon),
110 CASSERT((sizeof(smc_ctx_t) & 0x7U) == 0U, assert_smc_ctx_not_aligned);
111 CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch);
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_hwreq.h95 CASSERT(HWCG_PWR_SSUSB_P1 == 8, spm_pwr_status_err);
96 CASSERT(HWCG_PWR_PEXTP_PHY0 == 16, spm_pwr_status_err);
97 CASSERT(HWCG_PWR_MM_PROC == 24, spm_pwr_status_err);
151 CASSERT(PERI_REQ_EN_PWM == 8, spm_peri_req_en_err);
152 CASSERT(PERI_REQ_EN_SPI6 == 16, spm_peri_req_en_err);
153 CASSERT(PERI_REQ_EN_PEXTP0 == 24, spm_peri_req_en_err);
/rk3399_ARM-atf/include/common/
H A Dep_info.h47 CASSERT(ENTRY_POINT_INFO_PC_OFFSET ==
52 CASSERT(ENTRY_POINT_INFO_LR_SVC_OFFSET ==
57 CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \
61 CASSERT(sizeof(uintptr_t) ==
H A Druntime_svc.h93 CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC),
95 CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init),
97 CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle),
/rk3399_ARM-atf/lib/extensions/sve/
H A Dsve.c15 CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
16 CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
17 CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
/rk3399_ARM-atf/drivers/arm/css/scp/
H A Dcss_bom_bootloader.c56 CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2);
57 CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2);
59 CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow);
60 CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow);
/rk3399_ARM-atf/plat/brcm/board/common/
H A Dboard_common.c71 CASSERT((ARRAY_SIZE(plat_brcm_mmap) - 1) <= PLAT_BRCM_MMAP_ENTRIES,
73 CASSERT((PLAT_BRCM_MMAP_ENTRIES + BRCM_BL_REGIONS) <= MAX_MMAP_REGIONS,
/rk3399_ARM-atf/include/drivers/partition/
H A Dpartition.h20 CASSERT(PLAT_PARTITION_MAX_ENTRIES <= 128, assert_plat_partition_max_entries);
26 CASSERT((PLAT_PARTITION_BLOCK_SIZE == 512) ||
/rk3399_ARM-atf/plat/st/stm32mp1/sp_min/
H A Dsp_min_setup.c79 CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) &&
85 CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) &&
90 CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U,
/rk3399_ARM-atf/include/lib/el3_runtime/aarch64/
H A Dcontext.h366 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx),
369 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
373 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx),
377 CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx),
382 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
/rk3399_ARM-atf/include/lib/
H A Dcassert.h20 #define CASSERT(cond, msg) \ macro
/rk3399_ARM-atf/drivers/renesas/common/console/
H A Drcar_printf.c30 CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned);
31 CASSERT((RCAR_BL31_LOG_MAX & 0x7) == 0, assert_bl31_log_max_unaligned);
/rk3399_ARM-atf/plat/arm/board/morello/
H A Dmorello_def.h164 CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE,
167 CASSERT(sizeof(struct morello_firmware_version) == MORELLO_SDS_FIRMWARE_VERSION_SIZE,
H A Dmorello_topology.c11 CASSERT(PLATFORM_CORE_COUNT == 4U, assert_invalid_platform_core_count);
/rk3399_ARM-atf/include/lib/pmf/
H A Dpmf_helpers.h70 CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\
79 CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\
176 CASSERT(_flags != 0, select_proper_config); \
189 CASSERT(_flags != 0, select_proper_config); \
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_ras.c399 CASSERT(ARRAY_SIZE(per_core_ras_group) < RAS_NODE_INDEX_MAX,
405 CASSERT(ARRAY_SIZE(per_cluster_ras_group) < RAS_NODE_INDEX_MAX,
411 CASSERT(ARRAY_SIZE(scf_l3_ras_group) < RAS_NODE_INDEX_MAX,
417 CASSERT(ARRAY_SIZE(ccplex_ras_group) < RAS_NODE_INDEX_MAX,
472 CASSERT(ARRAY_SIZE(carmel_ras_records) < RAS_NODE_INDEX_MAX,
/rk3399_ARM-atf/plat/arm/common/
H A Darm_ccn.c23 CASSERT(PLAT_ARM_CLUSTER_COUNT == ARRAY_SIZE(master_to_rn_id_map),

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