1010d6ae3SXiaoDong Huang /* 2010d6ae3SXiaoDong Huang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3010d6ae3SXiaoDong Huang * 4010d6ae3SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5010d6ae3SXiaoDong Huang */ 6010d6ae3SXiaoDong Huang 7010d6ae3SXiaoDong Huang #ifndef __CPU_ON_FIXED_ADDR_H__ 8010d6ae3SXiaoDong Huang #define __CPU_ON_FIXED_ADDR_H__ 9010d6ae3SXiaoDong Huang 10010d6ae3SXiaoDong Huang /***************************************************************************** 11010d6ae3SXiaoDong Huang * define data offset in struct psram_data 12010d6ae3SXiaoDong Huang *****************************************************************************/ 13010d6ae3SXiaoDong Huang #define PSRAM_DT_SP 0x0 14010d6ae3SXiaoDong Huang #define PSRAM_DT_DDR_FUNC 0x8 15010d6ae3SXiaoDong Huang #define PSRAM_DT_DDR_DATA 0x10 16010d6ae3SXiaoDong Huang #define PSRAM_DT_DDRFLAG 0x18 17010d6ae3SXiaoDong Huang #define PSRAM_DT_MPIDR 0x1c 18010d6ae3SXiaoDong Huang #define PSRAM_DT_PM_FLAG 0x20 19010d6ae3SXiaoDong Huang #define PSRAM_DT_END 0x24 20010d6ae3SXiaoDong Huang 21010d6ae3SXiaoDong Huang /* reserve 4 byte */ 22010d6ae3SXiaoDong Huang #define PSRAM_DT_END_RES4 (PSRAM_DT_END + 4) 23010d6ae3SXiaoDong Huang 24010d6ae3SXiaoDong Huang #define PSRAM_DT_SIZE_WORDS (PSRAM_DT_END_RES4 / 4) 25010d6ae3SXiaoDong Huang 26010d6ae3SXiaoDong Huang #define PM_WARM_BOOT_SHT 0 27010d6ae3SXiaoDong Huang #define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT) 28010d6ae3SXiaoDong Huang 29d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 30010d6ae3SXiaoDong Huang 31010d6ae3SXiaoDong Huang struct psram_data_t { 32010d6ae3SXiaoDong Huang uint64_t sp; 33010d6ae3SXiaoDong Huang uint64_t ddr_func; 34010d6ae3SXiaoDong Huang uint64_t ddr_data; 35010d6ae3SXiaoDong Huang uint32_t ddr_flag; 36010d6ae3SXiaoDong Huang uint32_t boot_mpidr; 37010d6ae3SXiaoDong Huang uint32_t pm_flag; 38010d6ae3SXiaoDong Huang }; 39010d6ae3SXiaoDong Huang 40010d6ae3SXiaoDong Huang CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP, 41010d6ae3SXiaoDong Huang assert_psram_dt_sp_offset_mistmatch); 42010d6ae3SXiaoDong Huang CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC, 43010d6ae3SXiaoDong Huang assert_psram_dt_ddr_func_offset_mistmatch); 44010d6ae3SXiaoDong Huang CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA, 45010d6ae3SXiaoDong Huang assert_psram_dt_ddr_data_offset_mistmatch); 46010d6ae3SXiaoDong Huang CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG, 47010d6ae3SXiaoDong Huang assert_psram_dt_ddr_flag_offset_mistmatch); 48010d6ae3SXiaoDong Huang CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, 49010d6ae3SXiaoDong Huang assert_psram_dt_mpidr_offset_mistmatch); 50010d6ae3SXiaoDong Huang 51*7a5e90a8SScott Parlane extern struct psram_data_t sys_sleep_flag_sram; 52010d6ae3SXiaoDong Huang 53d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 54010d6ae3SXiaoDong Huang 55010d6ae3SXiaoDong Huang #endif 56