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Searched refs:parent_rate (Results 1 – 22 of 22) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dat91_h32mx.c18 unsigned long parent_rate) in clk_sama5d4_h32mx_get_rate() argument
24 return parent_rate / 2; in clk_sama5d4_h32mx_get_rate()
26 if (parent_rate > H32MX_MAX_FREQ) in clk_sama5d4_h32mx_get_rate()
29 return parent_rate; in clk_sama5d4_h32mx_get_rate()
34 unsigned long parent_rate) in clk_sama5d4_h32mx_set_rate() argument
39 if (parent_rate != rate && (parent_rate / 2) != rate) in clk_sama5d4_h32mx_set_rate()
42 if ((parent_rate / 2) == rate) in clk_sama5d4_h32mx_set_rate()
H A Dat91_plldiv.c16 unsigned long parent_rate) in clk_plldiv_get_rate() argument
22 return parent_rate / 2; in clk_plldiv_get_rate()
24 return parent_rate; in clk_plldiv_get_rate()
28 unsigned long parent_rate) in clk_plldiv_set_rate() argument
32 if (parent_rate != rate && (parent_rate / 2 != rate)) in clk_plldiv_set_rate()
36 parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); in clk_plldiv_set_rate()
H A Dat91_audio_pll.c151 static unsigned long clk_audio_pll_fout(unsigned long parent_rate, in clk_audio_pll_fout() argument
154 unsigned long long fr = (unsigned long long)parent_rate * fracr; in clk_audio_pll_fout()
158 return parent_rate * (nd + 1) + fr; in clk_audio_pll_fout()
162 unsigned long parent_rate) in clk_audio_pll_frac_get_rate() argument
166 return clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); in clk_audio_pll_frac_get_rate()
170 unsigned long parent_rate) in clk_audio_pll_pad_get_rate() argument
176 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); in clk_audio_pll_pad_get_rate()
182 unsigned long parent_rate) in clk_audio_pll_pmc_get_rate() argument
186 return parent_rate / (apmc_ck->qdpmc + 1); in clk_audio_pll_pmc_get_rate()
190 unsigned long parent_rate, in clk_audio_pll_frac_compute_frac() argument
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H A Dat91_peripheral.c34 unsigned long parent_rate = 0; in clk_sam9x5_peripheral_autodiv() local
42 parent_rate = clk_get_rate(parent); in clk_sam9x5_peripheral_autodiv()
43 if (!parent_rate) in clk_sam9x5_peripheral_autodiv()
47 if (parent_rate >> shift <= periph->range.max) in clk_sam9x5_peripheral_autodiv()
91 unsigned long parent_rate) in clk_sam9x5_peripheral_get_rate() argument
97 return parent_rate; in clk_sam9x5_peripheral_get_rate()
110 return parent_rate >> periph->div; in clk_sam9x5_peripheral_get_rate()
115 unsigned long parent_rate) in clk_sam9x5_peripheral_set_rate() argument
121 if (parent_rate == rate) in clk_sam9x5_peripheral_set_rate()
131 if (parent_rate >> shift == rate) { in clk_sam9x5_peripheral_set_rate()
H A Dat91_utmi.c40 unsigned long parent_rate = 0; in clk_utmi_enable() local
48 parent_rate = clk_get_rate(clk_parent); in clk_utmi_enable()
50 switch (parent_rate) { in clk_utmi_enable()
96 unsigned long parent_rate __unused) in clk_utmi_get_rate()
152 unsigned long parent_rate = 0; in clk_utmi_sama7g5_prepare() local
156 parent_rate = clk_get_rate(clk_parent); in clk_utmi_sama7g5_prepare()
158 switch (parent_rate) { in clk_utmi_sama7g5_prepare()
H A Dclk-sam9x60-pll.c86 unsigned long parent_rate) in sam9x60_frac_pll_recalc_rate() argument
90 return parent_rate * (frac->mul + 1) + in sam9x60_frac_pll_recalc_rate()
91 UDIV_ROUND_NEAREST((unsigned long long)parent_rate * frac->frac, in sam9x60_frac_pll_recalc_rate()
186 unsigned long parent_rate, in sam9x60_frac_pll_compute_mul_frac() argument
202 nmul = rate / parent_rate; in sam9x60_frac_pll_compute_mul_frac()
203 tmprate = parent_rate * nmul; in sam9x60_frac_pll_compute_mul_frac()
208 parent_rate); in sam9x60_frac_pll_compute_mul_frac()
210 tmprate += UDIV_ROUND_NEAREST((uint64_t)nfrac * parent_rate, in sam9x60_frac_pll_compute_mul_frac()
229 unsigned long parent_rate) in sam9x60_frac_pll_set_rate_chg() argument
236 ret = sam9x60_frac_pll_compute_mul_frac(frac, rate, parent_rate, true); in sam9x60_frac_pll_set_rate_chg()
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H A Dat91_pll.c105 unsigned long parent_rate) in clk_pll_get_rate() argument
112 return (parent_rate / pll->div) * (pll->mul + 1); in clk_pll_get_rate()
116 unsigned long parent_rate, in clk_pll_get_best_div_mul() argument
132 if (parent_rate < charac->input.min) in clk_pll_get_best_div_mul()
141 mindiv = (parent_rate * PLL_MUL_MIN) / rate; in clk_pll_get_best_div_mul()
145 if (parent_rate > charac->input.max) { in clk_pll_get_best_div_mul()
146 tmpdiv = DIV_ROUND_UP(parent_rate, charac->input.max); in clk_pll_get_best_div_mul()
158 maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate); in clk_pll_get_best_div_mul()
176 tmpmul = UDIV_ROUND_NEAREST(rate, parent_rate / tmpdiv); in clk_pll_get_best_div_mul()
177 tmprate = (parent_rate / tmpdiv) * tmpmul; in clk_pll_get_best_div_mul()
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H A Dat91_master.c50 unsigned long parent_rate) in clk_master_div_get_rate() argument
54 unsigned long rate = parent_rate; in clk_master_div_get_rate()
81 unsigned long parent_rate) in clk_master_pres_get_rate() argument
94 return UDIV_ROUND_NEAREST(parent_rate, pres); in clk_master_pres_get_rate()
212 unsigned long parent_rate) in clk_sama7g5_master_set_rate() argument
217 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_sama7g5_master_set_rate()
244 unsigned long parent_rate) in clk_sama7g5_master_get_rate() argument
247 unsigned long rate = parent_rate >> master->div; in clk_sama7g5_master_get_rate()
250 rate = parent_rate / 3; in clk_sama7g5_master_get_rate()
H A Dat91_usb.c27 unsigned long parent_rate) in at91sam9x5_clk_usb_get_rate() argument
35 return UDIV_ROUND_NEAREST(parent_rate, (usbdiv + 1)); in at91sam9x5_clk_usb_get_rate()
60 unsigned long parent_rate) in at91sam9x5_clk_usb_set_rate() argument
68 div = UDIV_ROUND_NEAREST(parent_rate, rate); in at91sam9x5_clk_usb_set_rate()
H A Dat91_programmable.c33 unsigned long parent_rate) in clk_programmable_get_rate() argument
41 rate = parent_rate / (PROG_PRES(layout, pckr) + 1); in clk_programmable_get_rate()
43 rate = parent_rate >> PROG_PRES(layout, pckr); in clk_programmable_get_rate()
94 unsigned long parent_rate) in clk_programmable_set_rate() argument
98 unsigned long div = parent_rate / rate; in clk_programmable_set_rate()
H A Dat91_main.c75 pmc_main_rc_osc_get_rate(struct clk *clk, unsigned long parent_rate __unused) in pmc_main_rc_osc_get_rate()
205 unsigned long parent_rate) in clk_main_get_rate() argument
209 if (parent_rate) in clk_main_get_rate()
210 return parent_rate; in clk_main_get_rate()
238 unsigned long parent_rate) in clk_sam9x5_main_get_rate() argument
242 return clk_main_get_rate(pmc->base, parent_rate); in clk_sam9x5_main_get_rate()
H A Dat91_generated.c60 clk_generated_get_rate(struct clk *clk, unsigned long parent_rate) in clk_generated_get_rate() argument
64 return UDIV_ROUND_NEAREST(parent_rate, gck->gckdiv + 1); in clk_generated_get_rate()
100 unsigned long parent_rate) in clk_generated_set_rate() argument
111 div = UDIV_ROUND_NEAREST(parent_rate, rate); in clk_generated_set_rate()
H A Dat91_cpu_opp.c48 unsigned long parent_rate) in cpu_opp_clk_set_rate() argument
60 return clk->parent->ops->set_rate(clk->parent, rate, parent_rate); in cpu_opp_clk_set_rate()
H A Dat91_sckc.c21 unsigned long parent_rate __unused) in sckc_get_rate()
/optee_os/core/drivers/clk/
H A Dclk-stm32-core.c270 static int divider_get_val(unsigned long rate, unsigned long parent_rate, in divider_get_val() argument
277 div = UDIV_ROUND_NEAREST((uint64_t)parent_rate, rate); in divider_get_val()
415 unsigned long parent_rate) in clk_stm32_divider_get_rate() argument
419 return stm32_div_get_rate(cfg->div_id, parent_rate); in clk_stm32_divider_get_rate()
424 unsigned long parent_rate) in clk_stm32_divider_set_rate() argument
428 return stm32_div_set_rate(cfg->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
460 unsigned long parent_rate) in clk_stm32_composite_get_rate() argument
465 return parent_rate; in clk_stm32_composite_get_rate()
467 return stm32_div_get_rate(cfg->div_id, parent_rate); in clk_stm32_composite_get_rate()
471 unsigned long parent_rate) in clk_stm32_composite_set_rate() argument
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H A Dclk.c76 unsigned long parent_rate = 0; in clk_compute_rate_no_lock() local
80 parent_rate = clk->parent->rate; in clk_compute_rate_no_lock()
84 clk->rate = clk->ops->get_rate(clk, parent_rate); in clk_compute_rate_no_lock()
86 clk->rate = parent_rate; in clk_compute_rate_no_lock()
215 unsigned long parent_rate = 0; in clk_set_rate_no_lock() local
218 parent_rate = clk_get_rate(clk->parent); in clk_set_rate_no_lock()
235 res = clk->ops->set_rate(clk, rate, parent_rate); in clk_set_rate_no_lock()
H A Dclk-stm32-core.h143 unsigned long parent_rate);
147 unsigned long parent_rate);
152 unsigned long parent_rate);
154 unsigned long parent_rate);
H A Dfixed_clk.c17 unsigned long parent_rate __unused) in fixed_clk_get_rate()
H A Dclk-stm32mp15.c966 static long get_timer_rate(long parent_rate, unsigned int apb_bus) in get_timer_rate() argument
991 return parent_rate; in get_timer_rate()
993 return parent_rate * (timgxpre + 1) * 2; in get_timer_rate()
1303 unsigned long parent_rate __unused) in clk_op_compute_rate()
H A Dclk-stm32mp21.c2020 unsigned long parent_rate) in clk_stm32_hse_div_set_rate() argument
2023 return clk_stm32_divider_set_rate(clk, rate, parent_rate); in clk_stm32_hse_div_set_rate()
2126 unsigned long parent_rate __unused) in clk_stm32_pll1_set_rate()
2374 unsigned long parent_rate) in clk_stm32_flexgen_set_rate() argument
2385 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv); in clk_stm32_flexgen_set_rate()
H A Dclk-stm32mp25.c2020 unsigned long parent_rate) in clk_stm32_hse_div_set_rate() argument
2022 return clk_stm32_divider_set_rate(clk, rate, parent_rate); in clk_stm32_hse_div_set_rate()
2119 unsigned long parent_rate __unused) in clk_stm32_pll1_set_rate()
2402 unsigned long parent_rate) in clk_stm32_flexgen_set_rate() argument
2410 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv); in clk_stm32_flexgen_set_rate()
/optee_os/core/include/drivers/
H A Dclk.h85 unsigned long parent_rate);
87 unsigned long parent_rate);