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Searched refs:io_write32 (Results 1 – 25 of 137) sorted by relevance

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/optee_os/core/arch/arm/plat-zynq7k/
H A Dmain.c60 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); in plat_primary_init_early()
66 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); in plat_primary_init_early()
67 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); in plat_primary_init_early()
68 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); in plat_primary_init_early()
74 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); in plat_primary_init_early()
75 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); in plat_primary_init_early()
76 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); in plat_primary_init_early()
77 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); in plat_primary_init_early()
79 io_write32(SLCR_UNLOCK, SLCR_UNLOCK_MAGIC); in plat_primary_init_early()
81 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); in plat_primary_init_early()
[all …]
/optee_os/core/arch/arm/plat-stm/
H A Dmain.c101 io_write32(pl310 + PL310_CTRL, 0); in arm_cl2_config()
104 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); in arm_cl2_config()
105 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); in arm_cl2_config()
106 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
107 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); in arm_cl2_config()
108 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
120 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); in plat_primary_init_early()
121 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); in plat_primary_init_early()
122 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); in plat_primary_init_early()
123 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); in plat_primary_init_early()
[all …]
/optee_os/core/arch/arm/plat-rockchip/
H A Dpsci_rk322x.c70 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_disable()
81 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_restore()
89 io_write32(va_base + CRU_MODE_CON, PLL_SLOW_MODE(pll)); in pll_power_down()
90 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_DOWN); in pll_power_down()
97 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_UP); in pll_power_up()
136 io_write32(va_base + CRU_CLKSEL_CON(0), BITS_WITH_WMASK(0, 0x1f, 0)); in plls_power_down()
137 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_power_down()
141 io_write32(va_base + CRU_CLKSEL_CON(10), in plls_power_down()
146 io_write32(va_base + CRU_CLKSEL_CON(0), BITS_WITH_WMASK(0, 0x1f, 8)); in plls_power_down()
147 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_power_down()
[all …]
H A Dplatform_rk322x.c28 io_write32(ddrsgrf_base + DDR_SGRF_DDR_CON(0), DDR_RGN0_NS); in platform_secure_init()
31 io_write32(sgrf_base + SGRF_SOC_CON(7), SLAVE_ALL_NS); in platform_secure_init()
32 io_write32(sgrf_base + SGRF_SOC_CON(8), SLAVE_ALL_NS); in platform_secure_init()
33 io_write32(sgrf_base + SGRF_SOC_CON(9), SLAVE_ALL_NS); in platform_secure_init()
34 io_write32(sgrf_base + SGRF_SOC_CON(10), SLAVE_ALL_NS); in platform_secure_init()
/optee_os/core/drivers/crypto/hisilicon/
H A Dhpre_main.c140 io_write32(qm->io_base + HPRE_CORE_ENB, HPRE_CLUSTER_CORE_MASK); in hpre_set_cluster()
141 io_write32(qm->io_base + HPRE_CORE_INI_CFG, 0x1); in hpre_set_cluster()
153 io_write32(qm->io_base + HPRE_CLKGATE_CTL, 0x0); in hpre_disable_clock_gate()
154 io_write32(qm->io_base + HPRE_PEH_CFG_AUTO_GATE, 0x0); in hpre_disable_clock_gate()
155 io_write32(qm->io_base + HPRE_CLUSTER_DYN_CTL, 0x0); in hpre_disable_clock_gate()
161 io_write32(qm->io_base + HPRE_CLKGATE_CTL, 0x1); in hpre_enable_clock_gate()
162 io_write32(qm->io_base + HPRE_PEH_CFG_AUTO_GATE, 0x1); in hpre_enable_clock_gate()
163 io_write32(qm->io_base + HPRE_CLUSTER_DYN_CTL, 0x1); in hpre_enable_clock_gate()
179 io_write32(qm->io_base + HPRE_CFG_AXCACHE, HPRE_AXCACHE_MASK); in hpre_engine_init()
180 io_write32(qm->io_base + HPRE_BD_ENDIAN, HPRE_BD_LITTLE_ENDIAN); in hpre_engine_init()
[all …]
H A Dsec_main.c94 io_write32(qm->io_base + SEC_DYNAMIC_GATE_V3, SEC_DYNAMIC_GATE_EN); in sec_enable_clock_gate()
95 io_write32(qm->io_base + SEC_CORE_AUTO_GATE_V3, SEC_CORE_AUTO_GATE_EN); in sec_enable_clock_gate()
111 io_write32(qm->io_base + SEC_MEM_START_INIT, 0x1); in sec_engine_init()
122 io_write32(qm->io_base + SEC_INTERFACE_USER_CTRL0, in sec_engine_init()
124 io_write32(qm->io_base + SEC_INTERFACE_USER_CTRL1, in sec_engine_init()
126 io_write32(qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS, in sec_engine_init()
128 io_write32(qm->io_base + SEC_SAA_EN, SEC_SAA_ENABLE); in sec_engine_init()
130 io_write32(qm->io_base + SEC_BD_ERR_CHK_EN0, SEC_BD_ERR_CHK0); in sec_engine_init()
132 io_write32(qm->io_base + SEC_BD_ERR_CHK_EN1, SEC_BD_ERR_CHK1); in sec_engine_init()
134 io_write32(qm->io_base + SEC_BD_ERR_CHK_EN2, SEC_BD_ERR_CHK2); in sec_engine_init()
[all …]
/optee_os/core/drivers/
H A Ddra7_rng.c86 io_write32(rng + RNG_ALARMMASK, 0x0); in dra7_rng_read64()
87 io_write32(rng + RNG_ALARMSTOP, 0x0); in dra7_rng_read64()
89 io_write32(rng + RNG_FRODETUNE, tune ^ alarm); in dra7_rng_read64()
91 io_write32(rng + RNG_FROENABLE, RNG_FRO_MASK); in dra7_rng_read64()
93 io_write32(rng + RNG_INTACK, SHUTDOWN_OFLO); in dra7_rng_read64()
102 io_write32(rng + RNG_INTACK, RNG_READY); in dra7_rng_read64()
140 io_write32(rng + RNG_SOFT_RESET_REG, RNG_SOFT_RESET); in dra7_rng_init()
147 io_write32(rng + RNG_SYS_CONFIG_REG, RNG_AUTOIDLE); in dra7_rng_init()
160 io_write32(rng + RNG_CONFIG, val); in dra7_rng_init()
163 io_write32(rng + RNG_FRODETUNE, 0x0); in dra7_rng_init()
[all …]
H A Dlpc_uart.c26 io_write32(LPC_CMD_REG_OFFSET + addr, LPC_SINGLE_READ); in lpc_byte_read()
28 io_write32(LPC_OP_LEN_REG_OFFSET + addr, 1); in lpc_byte_read()
29 io_write32(LPC_ADDR_REG_OFFSET + addr, UART_BASE + UART_LSR); in lpc_byte_read()
31 io_write32(LPC_START_REG_OFFSET + addr, 1); in lpc_byte_read()
41 io_write32(LPC_IRQ_ST_REG_OFFSET + addr, LPC_IRQ_ST_ON); in lpc_byte_read()
52 io_write32(LPC_CMD_REG_OFFSET + addr, LPC_SINGLE_WRITE); in lpc_byte_write()
53 io_write32(LPC_OP_LEN_REG_OFFSET + addr, 1); in lpc_byte_write()
54 io_write32(LPC_WDATA_REG_OFFSET + addr, data); in lpc_byte_write()
56 io_write32(LPC_ADDR_REG_OFFSET + addr, UART_BASE + UART_THR); in lpc_byte_write()
57 io_write32(LPC_START_REG_OFFSET + addr, 1); in lpc_byte_write()
[all …]
H A Datmel_tcb.c108 io_write32(tcb_base + TCB_WPMR, TCB_WPMR_WAKEY); in atmel_tcb_configure()
111 io_write32(tcb_base + TCB_IDR(0), 0xff); in atmel_tcb_configure()
112 io_write32(tcb_base + TCB_IDR(1), 0xff); in atmel_tcb_configure()
123 io_write32(tcb_base + TCB_CMR(0), in atmel_tcb_configure()
126 io_write32(tcb_base + TCB_RC(0), 0x80000000); in atmel_tcb_configure()
127 io_write32(tcb_base + TCB_RA(0), 0x1); in atmel_tcb_configure()
128 io_write32(tcb_base + TCB_CCR(0), TCB_CCR_CLKEN); in atmel_tcb_configure()
131 io_write32(tcb_base + TCB_CMR(1), TCB_CMR_XC1 | TCB_CMR_WAVE); in atmel_tcb_configure()
132 io_write32(tcb_base + TCB_CCR(1), TCB_CCR_CLKEN); in atmel_tcb_configure()
135 io_write32(tcb_base + TCB_BMR, TCB_BMR_TC1XC1S_TIOA0); in atmel_tcb_configure()
[all …]
H A Dhi16xx_uart.c86 io_write32(base + UART_THR, ch & 0xFF); in hi16xx_uart_putc()
122 io_write32(base + UART_FCR, UART_FCR_FIFO_EN); in hi16xx_uart_init()
125 io_write32(base + UART_LCR, UART_LCR_DLAB); in hi16xx_uart_init()
128 io_write32(base + UART_DLL, freq_div & 0xFF); in hi16xx_uart_init()
131 io_write32(base + UART_DLH, (freq_div >> 8) & 0xFF); in hi16xx_uart_init()
134 io_write32(base + UART_LCR, UART_LCR_DLS8); in hi16xx_uart_init()
137 io_write32(base + UART_IEL, 0); in hi16xx_uart_init()
H A Drockchip_otp.c68 io_write32(base + OTP_S_INT_ST, io_read32(base + OTP_S_INT_ST)); in rockchip_otp_read_secure()
71 io_write32(base + OTP_S_AUTO_CTRL, auto_ctrl_val); in rockchip_otp_read_secure()
74 io_write32(base + OTP_S_AUTO_EN, EN_ENABLE); in rockchip_otp_read_secure()
85 io_write32(base + OTP_S_INT_ST, io_read32(base + OTP_S_INT_ST)); in rockchip_otp_read_secure()
151 io_write32(base + OTP_S_INT_ST, io_read32(base + OTP_S_INT_ST)); in rockchip_otp_write_secure()
154 io_write32(base + OTP_S_AUTO_CTRL, auto_ctrl_val); in rockchip_otp_write_secure()
157 io_write32(base + OTP_S_PROG_DATA, new_val); in rockchip_otp_write_secure()
160 io_write32(base + OTP_S_AUTO_EN, EN_ENABLE); in rockchip_otp_write_secure()
172 io_write32(base + OTP_S_INT_ST, int_status); in rockchip_otp_write_secure()
H A Dimx_scu.c29 io_write32(scu_base + SCU_INV_SEC, SCU_INV_CTRL_INIT); in scu_init()
30 io_write32(scu_base + SCU_SAC, SCU_SAC_CTRL_INIT); in scu_init()
31 io_write32(scu_base + SCU_NSAC, SCU_NSAC_CTRL_INIT); in scu_init()
34 io_write32(scu_base + SCU_CTRL, io_read32(scu_base + SCU_CTRL) | 0x1); in scu_init()
H A Dpl011.c129 io_write32(base + UART_DR, ch); in pl011_putc()
136 io_write32(base + UART_IMSC, UART_IMSC_RXIM); in pl011_rx_intr_enable()
143 io_write32(base + UART_IMSC, 0); in pl011_rx_intr_disable()
167 io_write32(base + UART_RSR_ECR, 0); in pl011_init()
169 io_write32(base + UART_CR, 0); in pl011_init()
174 io_write32(base + UART_IBRD, divisor >> 6); in pl011_init()
175 io_write32(base + UART_FBRD, divisor & 0x3f); in pl011_init()
179 io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8); in pl011_init()
182 io_write32(base + UART_IMSC, UART_IMSC_RXIM); in pl011_init()
185 io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE); in pl011_init()
H A Dxiphera_trng.c59 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_READ); in xiphera_trng_read32()
60 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_ENABLE); in xiphera_trng_read32()
124 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_RESET); in xiphera_trng_probe()
149 io_write32(xiphera_trng_base + CONTROL_REG, in xiphera_trng_probe()
151 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_ENABLE); in xiphera_trng_probe()
152 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_ZEROIZE); in xiphera_trng_probe()
170 io_write32(xiphera_trng_base + CONTROL_REG, HOST_TO_TRNG_ACK_ZEROIZE); in xiphera_trng_probe()
H A Dsp805_wdt.c52 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_config()
53 io_write32(base + WDT_LOAD_OFFSET, pd->load_val); in sp805_config()
54 io_write32(base + WDT_INTCLR_OFFSET, WDT_INT_CLR); in sp805_config()
57 io_write32(base + WDT_CONTROL_OFFSET, in sp805_config()
60 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_config()
80 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_disable()
81 io_write32(base + WDT_CONTROL_OFFSET, 0); in sp805_disable()
82 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_disable()
H A Dgic.c206 io_write32(gicc_base + GICC_CTLR, 0); in probe_max_it()
214 io_write32(gicd_base + GICD_ISENABLER(i), 0xffffffff); in probe_max_it()
216 io_write32(gicd_base + GICD_ICENABLER(i), ~old_reg); in probe_max_it()
228 io_write32(gicc_base + GICC_CTLR, old_ctlr); in probe_max_it()
276 io_write32(gicr_base + GICR_ICENABLER0, BIT32(n)); in gicv3_sync_redist_config()
282 io_write32(gicr_base + GICR_ICPENDR0, BIT32(n)); in gicv3_sync_redist_config()
295 io_write32(gicr_base + GICR_IGROUPR0, grp0); in gicv3_sync_redist_config()
296 io_write32(gicr_base + GICR_IGRPMODR0, gmod0); in gicv3_sync_redist_config()
297 io_write32(gicr_base + GICR_ISENABLER0, gd->per_cpu_enable); in gicv3_sync_redist_config()
319 io_write32(gd->gicd_base + GICD_ICENABLER(0), BIT(n)); in gic_legacy_sync_dist_config()
[all …]
H A Dbcm_sotp.c105 io_write32((bcm_sotp_base + SOTP_ADDR), reg_val); in bcm_iproc_sotp_mem_read()
107 io_write32((bcm_sotp_base + SOTP_CTRL_0), reg_val); in bcm_iproc_sotp_mem_read()
169 io_write32(bcm_sotp_base + SOTP_CHIP_CTRL, chip_ctrl); in bcm_iproc_sotp_mem_write()
198 io_write32(bcm_sotp_base + SOTP_CTRL_0, SOTP_PROG_ENABLE << 1); in bcm_iproc_sotp_mem_write()
208 io_write32(bcm_sotp_base + SOTP_WRDATA_0, prog_array[loop]); in bcm_iproc_sotp_mem_write()
239 io_write32(bcm_sotp_base + SOTP_ADDR, in bcm_iproc_sotp_mem_write()
243 io_write32(bcm_sotp_base + SOTP_WRDATA_0, wdata & SOTP_ROW_DATA_MASK); in bcm_iproc_sotp_mem_write()
246 io_write32(bcm_sotp_base + SOTP_WRDATA_1, in bcm_iproc_sotp_mem_write()
250 io_write32(bcm_sotp_base + SOTP_CTRL_0, SOTP_PROG_WORD << 1); in bcm_iproc_sotp_mem_write()
274 io_write32(bcm_sotp_base + SOTP_CHIP_CTRL, chip_ctrl_default); in bcm_iproc_sotp_mem_write()
H A Dzynqmp_csu_aes.c218 io_write32(csu + ZYNQMP_CSU_SSS_CFG_OFFSET, in aes_prepare_op()
222 io_write32(aes + AES_RESET_OFFSET, AES_RESET_SET); in aes_prepare_op()
223 io_write32(aes + AES_RESET_OFFSET, AES_RESET_CLR); in aes_prepare_op()
226 io_write32(aes + AES_KEY_CLR_OFFSET, 0); in aes_prepare_op()
227 io_write32(aes + AES_KEY_SRC_OFFSET, key); in aes_prepare_op()
228 io_write32(aes + AES_KEY_LOAD_OFFSET, AES_KEY_LOAD); in aes_prepare_op()
236 io_write32(aes + AES_CFG_OFFSET, in aes_prepare_op()
240 io_write32(csu + ZYNQMP_CSU_DMA_RESET_OFFSET, ZYNQMP_CSU_DMA_RESET_SET); in aes_prepare_op()
241 io_write32(csu + ZYNQMP_CSU_DMA_RESET_OFFSET, ZYNQMP_CSU_DMA_RESET_CLR); in aes_prepare_op()
244 io_write32(aes + AES_START_MSG_OFFSET, AES_START_MSG); in aes_prepare_op()
[all …]
/optee_os/core/arch/arm/plat-sam/
H A Dsam_pl310.c60 io_write32(pl310_base + PL310_CTRL, 0); in arm_cl2_config()
61 io_write32(sam_sfr_base() + AT91_SFR_L2CC_HRAMC, 0x1); in arm_cl2_config()
62 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
63 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); in arm_cl2_config()
64 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
73 io_write32(pl310_base + PL310_CTRL, 1); in arm_cl2_enable()
98 io_write32(base + PL310_DEBUG_CTRL, 0); in pl310_enable_writeback()
108 io_write32(base + PL310_DEBUG_CTRL, val); in pl310_disable_writeback()
/optee_os/core/arch/arm/plat-imx/
H A Dimx_pl310.c34 io_write32(pl310_base + PL310_CTRL, 0); in arm_cl2_config()
36 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); in arm_cl2_config()
37 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); in arm_cl2_config()
38 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
59 io_write32(pl310_base + PL310_PREFETCH_CTRL, val); in arm_cl2_config()
61 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
72 io_write32(pl310_base + PL310_CTRL, 1); in arm_cl2_enable()
112 io_write32(base + PL310_DEBUG_CTRL, 0); in pl310_enable_writeback()
122 io_write32(base + PL310_DEBUG_CTRL, val); in pl310_disable_writeback()
/optee_os/core/arch/arm/plat-hikey/
H A Dmain.c69 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); in spi_init()
88 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); in spi_init()
105 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); in spi_init()
106 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); in spi_init()
107 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); in spi_init()
108 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); in spi_init()
111 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); in spi_init()
112 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); in spi_init()
113 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); in spi_init()
114 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); in spi_init()
/optee_os/core/arch/arm/plat-telechips/drivers/
H A Dtcc_otp.c87 io_write32(reg + OTP_ADDRESS, offset); in tcc_otp_read_128()
88 io_write32(reg + OTP_CONTROL, CTRL_CMD_READ | CTRL_START); in tcc_otp_read_128()
130 io_write32(reg + OTP_ADDRESS, offset); in tcc_otp_write_128()
131 io_write32(reg + PROG_DATA_PAYLOAD0, buf[0]); in tcc_otp_write_128()
132 io_write32(reg + PROG_DATA_PAYLOAD1, buf[1]); in tcc_otp_write_128()
133 io_write32(reg + PROG_DATA_PAYLOAD2, buf[2]); in tcc_otp_write_128()
134 io_write32(reg + PROG_DATA_PAYLOAD3, buf[3]); in tcc_otp_write_128()
135 io_write32(reg + PROG_ADMIN_INFO0, 0); in tcc_otp_write_128()
136 io_write32(reg + PROG_ADMIN_INFO1, 0); in tcc_otp_write_128()
137 io_write32(reg + PROG_ADMIN_INFO2, 0); in tcc_otp_write_128()
[all …]
/optee_os/core/arch/arm/plat-k3/drivers/
H A Deip76d_trng.c79 io_write32(rng + RNG_CONFIG, val); in eip76d_rng_init_seq()
82 io_write32(rng + RNG_FRODETUNE, 0x0); in eip76d_rng_init_seq()
85 io_write32(rng + RNG_FROENABLE, 0xffffff); in eip76d_rng_init_seq()
87 io_write32(rng + RNG_CONTROL, ENABLE_TRNG); in eip76d_rng_init_seq()
104 io_write32(rng + RNG_ALARMMASK, 0x0); in eip76d_rng_read128()
105 io_write32(rng + RNG_ALARMSTOP, 0x0); in eip76d_rng_read128()
107 io_write32(rng + RNG_FRODETUNE, tune ^ alarm); in eip76d_rng_read128()
109 io_write32(rng + RNG_FROENABLE, RNG_FRO_MASK); in eip76d_rng_read128()
111 io_write32(rng + RNG_INTACK, SHUTDOWN_OFLO); in eip76d_rng_read128()
122 io_write32(rng + RNG_INTACK, RNG_READY); in eip76d_rng_read128()
/optee_os/core/arch/arm/plat-ti/
H A Dsm_platform_handler_a9.c38 io_write32(pl310_base() + PL310_DEBUG_CTRL, smc_args->a1); in ti_sip_handler()
47 io_write32(pl310_base() + PL310_CTRL, smc_args->a1); in ti_sip_handler()
51 io_write32(pl310_base() + PL310_AUX_CTRL, smc_args->a1); in ti_sip_handler()
55 io_write32(pl310_base() + PL310_TAG_RAM_CTRL, smc_args->a1); in ti_sip_handler()
56 io_write32(pl310_base() + PL310_DATA_RAM_CTRL, smc_args->a2); in ti_sip_handler()
60 io_write32(pl310_base() + PL310_PREFETCH_CTRL, smc_args->a1); in ti_sip_handler()
/optee_os/core/arch/arm/plat-bcm/
H A Dbcm_elog.c32 io_write32(base + BCM_ELOG_OFF_OFFSET, offset); in bcm_elog_putchar()
33 io_write32(base + BCM_ELOG_LEN_OFFSET, len); in bcm_elog_putchar()
54 io_write32(base + BCM_ELOG_SIG_OFFSET, BCM_ELOG_SIG_VAL); in bcm_elog_init()
55 io_write32(base + BCM_ELOG_OFF_OFFSET, BCM_ELOG_HEADER_LEN); in bcm_elog_init()
56 io_write32(base + BCM_ELOG_LEN_OFFSET, 0); in bcm_elog_init()

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