1*40c3f16eSClement Faure // SPDX-License-Identifier: BSD-2-Clause 2*40c3f16eSClement Faure /* 3*40c3f16eSClement Faure * Copyright 2017-2019, 2023 NXP 4*40c3f16eSClement Faure * 5*40c3f16eSClement Faure */ 6*40c3f16eSClement Faure 7*40c3f16eSClement Faure #include <imx.h> 8*40c3f16eSClement Faure #include <initcall.h> 9*40c3f16eSClement Faure #include <io.h> 10*40c3f16eSClement Faure #include <kernel/tz_ssvce_def.h> 11*40c3f16eSClement Faure #include <mm/core_memprot.h> 12*40c3f16eSClement Faure 13*40c3f16eSClement Faure /* Invalidate all registers */ 14*40c3f16eSClement Faure #define SCU_INV_CTRL_INIT 0xFFFFFFFF 15*40c3f16eSClement Faure /* Both secure CPU access SCU */ 16*40c3f16eSClement Faure #define SCU_SAC_CTRL_INIT 0x0000000F 17*40c3f16eSClement Faure /* Both non-secure CPU access SCU, private and global timer */ 18*40c3f16eSClement Faure #define SCU_NSAC_CTRL_INIT 0x00000FFF 19*40c3f16eSClement Faure scu_init(void)20*40c3f16eSClement Faurestatic TEE_Result scu_init(void) 21*40c3f16eSClement Faure { 22*40c3f16eSClement Faure vaddr_t scu_base = core_mmu_get_va(SCU_BASE, MEM_AREA_IO_SEC, 23*40c3f16eSClement Faure SCU_SIZE); 24*40c3f16eSClement Faure 25*40c3f16eSClement Faure if (!scu_base) 26*40c3f16eSClement Faure return TEE_ERROR_GENERIC; 27*40c3f16eSClement Faure 28*40c3f16eSClement Faure /* SCU config */ 29*40c3f16eSClement Faure io_write32(scu_base + SCU_INV_SEC, SCU_INV_CTRL_INIT); 30*40c3f16eSClement Faure io_write32(scu_base + SCU_SAC, SCU_SAC_CTRL_INIT); 31*40c3f16eSClement Faure io_write32(scu_base + SCU_NSAC, SCU_NSAC_CTRL_INIT); 32*40c3f16eSClement Faure 33*40c3f16eSClement Faure /* SCU enable */ 34*40c3f16eSClement Faure io_write32(scu_base + SCU_CTRL, io_read32(scu_base + SCU_CTRL) | 0x1); 35*40c3f16eSClement Faure 36*40c3f16eSClement Faure return TEE_SUCCESS; 37*40c3f16eSClement Faure } 38*40c3f16eSClement Faure driver_init(scu_init); 39