core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special

core: do not acknowledge end of interrupt for special GIC interrupt IDs

According to the ARM documentation for GICV2/3/4, there is no need to
write to the end of interrupt register for some special IDs. Apply this
recommendation to avoid writing to IO memory in this time sensitive
sequence.

Also distinguish unhandled interrupts with an error log.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt d

core: interrupt: rename .add handler to .configure

Rename field add of struct itr_ops to configure for consistency
since that handler is used the configure the interrupt. Update
existing interrupt drivers accordingly.

By the way fix inline comment spelling typo (s/contrainsts/constraints/).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gic: minor coding style fixes

Fix minor issues coding style issue for uninitialized local variable
and trace message formatting. No functional change.

Signed-off-by: Etienne Carriere <etie

drivers: gic: minor coding style fixes

Fix minor issues coding style issue for uninitialized local variable
and trace message formatting. No functional change.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gic: allow detection type configuration

Allow consumers to configure SPI interrupts when the provided type
is not IRQ_TYPE_NONE. The allowed value are then IRQ_TYPE_EDGE_RISING
and IRQ_TYPE

drivers: gic: allow detection type configuration

Allow consumers to configure SPI interrupts when the provided type
is not IRQ_TYPE_NONE. The allowed value are then IRQ_TYPE_EDGE_RISING
and IRQ_TYPE_LEVEL_HIGH, as per Arm GIC specification.

This change fixes an issue when using interrupt_dt_get_by_index()
or interrupt_dt_get_by_name() since these API functions tell the
interrupt is configured from DT phandle arguments whereas GIC driver
did not consider the interrupt detection type even if set in the
consumer DT node property.

Fixes: 14885eb1688b ("drivers: gic: register to dt_driver")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: gic: Dynamically assign interrupts to non-secure world

Add gic_spi_release_to_ns() API function in GIC driver to release an
interrupt to Non secure settings. This functionality is essential

drivers: gic: Dynamically assign interrupts to non-secure world

Add gic_spi_release_to_ns() API function in GIC driver to release an
interrupt to Non secure settings. This functionality is essential for
scenarios where a specific interrupt needs to be dynamically set to
either Group 1 Secure (G1S) or Group 1 Non-Secure (G1NS) at different
times.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: gic: accept GIC version 4 if CFG_ARM_GICV3 is enabled

GIC v4 is backwards compatible with GIC v3, Accept GIC
version 4 if CFG_ARM_GICV3 is enabled.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy

core: gic: accept GIC version 4 if CFG_ARM_GICV3 is enabled

GIC v4 is backwards compatible with GIC v3, Accept GIC
version 4 if CFG_ARM_GICV3 is enabled.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updat

core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updates are still being propagated. Add checks for this
after each write to GICR_ICENABLER0 to make sure that the system is
consistent before continuing.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be sync

core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be synchronized to all CPUs in the same way. Add support to
synchronize needed PPI configuration to other CPUs.

The configuration that needs to be synchronized to other CPUs should
ideally not be changed once the primary CPU has booted. So add a check
in gic_op_enable() to catch this.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.

core: remove unused deprecated gic_cpu_init()

Remove the unused deprecated function gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so a

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so allow version 1 also.

Fixes: 69171bec89ce ("core: gic: check gic version")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Andrew Davis <afd@ti.com>

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core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using th

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using the redistributor is optional if gic_init_donate_sgi_to_ns() isn't
called. So allow the GICR base address to be passed as zero if
gic_init_donate_sgi_to_ns() isn't called. However,
gic_init_donate_sgi_to_ns() will panic if called without a previously
configured GICR base address.

Fixes: 05089e5f9a56 ("core: gic: use redistributor CPU interface")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: add gic_init_donate_sgi_to_ns()

Adds gic_init_donate_sgi_to_ns() which changes a secure SGI to become
non-secure.

Secure world currently has a few SGIs to spare while normal world
typica

core: gic: add gic_init_donate_sgi_to_ns()

Adds gic_init_donate_sgi_to_ns() which changes a secure SGI to become
non-secure.

Secure world currently has a few SGIs to spare while normal world
typically have reserved each of the non-secure SGIs for different
purposes.

In case another non-secure SGI is needed secure world can donate one of
its unused SGIs. This configuration will then deviate from the standard
GIC configuration where SGI ID0-ID7 are non-secure and ID8-ID15 are
secure.

Platforms using gic_init_donate_sgi_to_ns() should also use
gic_init_per_cpu() instead of the deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: deprecate gic_cpu_init()

Deprecates gic_cpu_init() in favor of the new function
gic_init_per_cpu(). gic_cpu_init() is only supposed to be called by
secondary CPUs in non-TF-A configurations w

core: deprecate gic_cpu_init()

Deprecates gic_cpu_init() in favor of the new function
gic_init_per_cpu(). gic_cpu_init() is only supposed to be called by
secondary CPUs in non-TF-A configurations while gic_init_per_cpu()
should be called by all secondary CPUs. gic_init_per_cpu() itself takes
CFG_WITH_ARM_TRUSTED_FW into account instead of having each platform
doing that.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: use redistributor CPU interface

GICv3 has a redistributor CPU interface that until now hasn't been used.
To prepare for coming patches that need to access the redistributor
initialize a l

core: gic: use redistributor CPU interface

GICv3 has a redistributor CPU interface that until now hasn't been used.
To prepare for coming patches that need to access the redistributor
initialize a list with each CPU specific redistributor address. A new
function gic_init_v3() is added with a parameter for the redistributor
base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: check gic version

Adds a check to see that the version of the GIC matches the expected
version.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <e

core: gic: check gic version

Adds a check to see that the version of the GIC matches the expected
version.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: gic: use DT bindings

Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: gic: use DT bindings

Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: gic: register to dt_driver

Registers GIC driver as an interrupt controller in DT_DRIVER
providers when DT is supported. This change allows interrupt
consumer nodes to leverage interrupts an

drivers: gic: register to dt_driver

Registers GIC driver as an interrupt controller in DT_DRIVER
providers when DT is supported. This change allows interrupt
consumer nodes to leverage interrupts and interrupts-extended
properties DT bindings for their device drivers to retrieve
their interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt_raise_sgi() updates

Adds ITR_CPU_MASK_TO_THIS_CPU and ITR_CPU_MASK_TO_OTHER_CPUS to simplify
targeting CPUs in some use cases. The cpu_mask parameter is changed to a
uint32_t to make

core: interrupt_raise_sgi() updates

Adds ITR_CPU_MASK_TO_THIS_CPU and ITR_CPU_MASK_TO_OTHER_CPUS to simplify
targeting CPUs in some use cases. The cpu_mask parameter is changed to a
uint32_t to make room for the two new flags.

The gic driver is updated to support this new flag.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver,

drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver, the HFIC driver and Atmel SAIC driver.

Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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driver: gic: support sgi raise for gicv3

Use write_icc_sgi1r() and write_icc_asgi1r() to raise SGI
for gicv3.
And move the assertion from gic_it_raise_sgi() to
the caller function to improve the rea

driver: gic: support sgi raise for gicv3

Use write_icc_sgi1r() and write_icc_asgi1r() to raise SGI
for gicv3.
And move the assertion from gic_it_raise_sgi() to
the caller function to improve the readability
of gic_it_raise_sgi().

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: gic: implement mask/unmask handler

Implements GIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers.

Reviewed-by: Jens Wiklander <jens.wiklander@li

driver: gic: implement mask/unmask handler

Implements GIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gic: prevent accessing unimplemented GIC registers

The GIC method for probing for the highest implemented interrupt ignored
is done by writing & reading to GIC registers GICD_ISENABLER<n> &

drivers: gic: prevent accessing unimplemented GIC registers

The GIC method for probing for the highest implemented interrupt ignored
is done by writing & reading to GIC registers GICD_ISENABLER<n> &
GICD_ICENABLER<n> that are not always implemented. This causes an
error indication in GIC register GICT_ERR0_STATUS. To prevent this,
Check in GIC register GICD_TYPER how many SPI blocks are implemented
and access only implemented registers.

Signed-off-by: Izhar Nevo <inevo@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <je

core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by:

core: interrupt: rename itr_core_handler()

Renames itr_core_handler() to interrupt_main_handler() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This chang

drivers: gic: factorize call to gic_init() or gic_init_base_addr()

Platforms call either gic_init() or gic_init_base_addr() depending
on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This change
factorize this logic from gic_init() implementation and makes
gic_init_base_addr() local to gic.c.

For that purpose functions gic_init_base_address() and gic_dt_get_irq()
are moved inside gic.c source file.
source file.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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