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Searched refs:io_clrbits32 (Results 1 – 25 of 63) sorted by relevance

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/optee_os/core/drivers/
H A Dbcm_sotp.c96 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
123 io_clrbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_read()
138 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), in bcm_iproc_sotp_mem_read()
190 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
194 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
227 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
267 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, in bcm_iproc_sotp_mem_write()
271 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); in bcm_iproc_sotp_mem_write()
H A Dls_gpio.c72 io_clrbits32(gpio_data_addr, PIN_SHIFT(gpio_pin)); in ls_gpio_set_value()
121 io_clrbits32(gpio_dir_addr, PIN_SHIFT(gpio_pin)); in ls_gpio_set_direction()
170 io_clrbits32(gpio_ier_addr, PIN_SHIFT(gpio_pin)); in gpio_set_interrupt()
H A Dimx_snvs.c105 io_clrbits32(base + SNVS_LPMKCR, SNVS_LPMKCR_MKCR_MKS_SEL); in set_mks_otpmk()
106 io_clrbits32(base + SNVS_HPLR, SNVS_HPLR_MKS_SL); in set_mks_otpmk()
H A Dzynqmp_csudma.c103 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
105 io_clrbits32(dma + CSUDMA_CTRL_OFFSET, CSUDMA_CTRL_ENDIAN_MASK); in zynqmp_csudma_unprepare()
H A Datmel_piobu.c130 io_clrbits32(piobu_addr, SECUMOD_PIOBU_SOD); in secumod_gpio_set_value()
176 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in secumod_gpio_set_direction()
220 io_clrbits32(niepr_addr, SECUMOD_PIN_VAL(gpio_pin)); in secumod_gpio_set_interrupt()
320 io_clrbits32(piobu_addr, SECUMOD_PIOBU_OUTPUT); in secumod_cfg_input_pio()
H A Datmel_rstc.c115 io_clrbits32(rstc_base + RESET_OFFSET(id), BIT(RESET_BIT_POS(id))); in reset_deassert()
172 io_clrbits32(rstc_base + AT91_RSTC_GRSTR, in sam_rstc_usb_por()
H A Dstm32_rng.c138 io_clrbits32(rng_base + RNG_CR, RNG_CR_CONDRST); in conceal_seed_error_cond_reset()
146 io_clrbits32(rng_base + RNG_SR, RNG_SR_SEIS); in conceal_seed_error_cond_reset()
198 io_clrbits32(rng_base + RNG_SR, RNG_SR_SEIS); in conceal_seed_error_sw_reset()
548 io_clrbits32(rng_base + RNG_CR, RNG_CR_CONDRST); in stm32_rng_pm_suspend()
557 io_clrbits32(rng_base + RNG_CR, RNG_CR_RNGEN); in stm32_rng_pm_suspend()
H A Dbcm_hwrng.c40 io_clrbits32(bcm_hwrng_base + in bcm_hwrng_reset()
H A Dstm32_hsem.c85 io_clrbits32(hsem_d->base + HSEM_CnCIDCFGR(i + 1), in apply_rif_config()
90 io_clrbits32(hsem_d->base + HSEM_GpCIDCFGR(i), in apply_rif_config()
H A Dbcm_gpio.c74 io_clrbits32(gc->base + offset, BIT(shift)); in iproc_clr_bit()
171 io_clrbits32(regaddr, BIT(shift)); in iproc_gpio_set_secure()
/optee_os/core/arch/arm/plat-sunxi/
H A Dpsci.c101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
118 io_clrbits32(base + REG_PRCM_CPU_PWROFF, BIT32(core_idx)); in psci_cpu_on()
H A Dmain.c173 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK); in smc_init()
/optee_os/core/drivers/clk/sam/
H A Dat91_audio_pll.c79 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_enable()
128 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
131 io_clrbits32(frac->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_frac_disable()
139 io_clrbits32(apad_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pad_disable()
147 io_clrbits32(apmc_ck->base + AT91_PMC_AUDIO_PLL0, in clk_audio_pll_pmc_disable()
H A Dphy-sama7-utmi-clk.c32 io_clrbits32(utmi->base + SAMA7_SFR_UTMI0R(id), in sama7_utmi_clk_enable()
/optee_os/core/drivers/counter/
H A Dstm32_stgen.c104 io_clrbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stm32_stgen_pm_suspend()
128 io_clrbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stm32_stgen_pm_resume()
230 io_clrbits32(stgen_d.base + STGENC_CNTCR, STGENC_CNTCR_EN); in stgen_probe()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
H A Dhal_clk.c20 io_clrbits32(pcc3_base + PCC_CAAM, PCC_ENABLE_CLOCK); in caam_hal_clk_enable()
/optee_os/core/drivers/pm/imx/
H A Dgpcv2.c30 io_clrbits32(va + offset, GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc()
H A Dsrc.c77 io_clrbits32(va + SRC_A7RCR1, in imx_src_shutdown_core()
/optee_os/core/arch/arm/plat-sam/
H A Dsam_sfr.c39 io_clrbits32(sam_sfr_base() + AT91_SFR_OHCIICR, in atmel_sfr_set_usb_suspend()
/optee_os/core/arch/arm/plat-hisilicon/
H A Dpsci.c88 io_clrbits32(crg + REG_CPU_SUSSYS_RESET, RELEASE_CORE_MASK); in psci_cpu_on()
/optee_os/core/drivers/firewall/
H A Dstm32_risab.c346 io_clrbits32(base + _RISAB_PGy_CIDCFGR(i), in apply_rif_config()
348 io_clrbits32(base + _RISAB_PGy_SECCFGR(i), in apply_rif_config()
350 io_clrbits32(base + _RISAB_PGy_PRIVCFGR(i), in apply_rif_config()
354 io_clrbits32(base + _RISAB_CIDxRDCFGR(i), UINT32_MAX); in apply_rif_config()
355 io_clrbits32(base + _RISAB_CIDxWRCFGR(i), UINT32_MAX); in apply_rif_config()
356 io_clrbits32(base + _RISAB_CIDxPRIVCFGR(i), UINT32_MAX); in apply_rif_config()
565 io_clrbits32(risab_base(risab_d), _RISAB_CR_SRWIAD); in disable_srwiad_if_unset()
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c90 io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); in rzn1_cm3_start()
/optee_os/core/drivers/imx/mu/
H A Dimx_mu_8q.c57 io_clrbits32(base + MU_ACR_OFFSET, in imx_mu_plat_init()
/optee_os/core/drivers/regulator/
H A Dstm32mp13_regulator_iod.c98 io_clrbits32(pwr_reg, iod->enable_mask); in iod_set_state()
104 io_clrbits32(pwr_reg, iod->enable_mask | iod->valid_mask); in iod_set_state()
/optee_os/core/arch/arm/plat-stm32mp2/drivers/
H A Dstm32mp25_syscfg.c72 io_clrbits32(addr, SYSCFG_SAFERSTCR_EN); in stm32mp25_syscfg_set_safe_reset()

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