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Searched refs:IMSG (Results 1 – 25 of 71) sorted by relevance

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/optee_os/core/arch/arm/plat-nuvoton/
H A Dmain.c48 IMSG(COLOR_MAGENTA); in print_version()
49 IMSG(">================================================"); in print_version()
50 IMSG("OP-TEE OS Version %s", core_v_str); in print_version()
51 IMSG(">================================================"); in print_version()
52 IMSG(COLOR_NORMAL); in print_version()
97 IMSG("HUK Initialized"); in tee_otp_get_hw_unique_key()
/optee_os/core/arch/riscv/kernel/
H A Dboot.c233 IMSG("OP-TEE version: %s", core_v_str); in boot_init_primary_runtime()
235 IMSG("WARNING: This OP-TEE configuration might be insecure!"); in boot_init_primary_runtime()
236 …IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines… in boot_init_primary_runtime()
238 IMSG("Primary CPU0 (hart%"PRIu32") initializing", in boot_init_primary_runtime()
256 IMSG("Primary CPU0 (hart%"PRIu32") initialized", in boot_init_primary_final()
268 IMSG("Secondary CPU%zu (hart%"PRIu32") initializing", in init_secondary_helper()
283 IMSG("Secondary CPU%zu (hart%"PRIu32") initialized", in init_secondary_helper()
/optee_os/core/arch/arm/plat-k3/drivers/
H A Dsa2ul.c66 IMSG("Activated SA2UL device"); in sa2ul_init()
79 IMSG("Fixing SA2UL firewall owner for GP device"); in sa2ul_init()
133 IMSG("Enabled firewalls for SA2UL TRNG device"); in sa2ul_init()
138 IMSG("Enabling SA2UL TRNG engine"); in sa2ul_init()
147 IMSG("SA2UL Drivers initialized"); in sa2ul_init()
H A Ddthev2.c32 IMSG("DTHEv2 Drivers initialized"); in dthev2_init()
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dmain.c46 IMSG("Platform stm32mp2: flavor %s - DT %s", ID2STR(PLATFORM_FLAVOR), in platform_banner()
95 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); in plat_console_init()
120 IMSG("DTB disables console"); in init_console_from_dt()
129 IMSG("DTB enables console"); in init_console_from_dt()
198 IMSG("Forced system reset: %s", str); in do_reset()
/optee_os/core/arch/arm/plat-k3/
H A Dmain.c93 IMSG("Secure Board Configuration Software: Rev %"PRIu32, in secure_boot_information()
97 IMSG("Secure Boot Keys: Count %"PRIu32 ", Rev %"PRIu32, in secure_boot_information()
121 IMSG("HUK Initialized"); in tee_otp_get_hw_unique_key()
/optee_os/core/kernel/
H A Dconsole.c65 IMSG("Disabling output console"); in console_runtime_set()
115 IMSG("Switching off console"); in get_console_node_from_dt()
192 IMSG("Switching console to device: %s", uart); in configure_console_from_dt()
H A Dshow_conf.c14 IMSG("Contents of conf.mk (decode with 'base64 -d | xz -d'):"); in show_conf()
H A Dpanic.c22 IMSG("Halting CPU %zu", get_core_pos()); in multi_core_halt_it_handler()
/optee_os/core/arch/riscv/tee/
H A Dentry_fast.c64 IMSG("Reserved shared memory is %sabled", res_shm_en ? "en" : "dis"); in tee_entry_exchange_capabilities()
71 IMSG("Dynamic shared memory is %sabled", dyn_shm_en ? "en" : "dis"); in tee_entry_exchange_capabilities()
75 IMSG("Normal World virtualization support is %sabled", in tee_entry_exchange_capabilities()
84 IMSG("Asynchronous notifications are %sabled", in tee_entry_exchange_capabilities()
/optee_os/core/drivers/crypto/se050/glue/
H A Di2c_stm32.c62 IMSG("SE05X ignoring CFG_CORE_SE05X_BAUDRATE, use DTB"); in dt_i2c_bus_config()
64 IMSG("SE05x ignoring CFG_CORE_SE05X_BAUDRATE, use built-in"); in dt_i2c_bus_config()
/optee_os/core/arch/arm/plat-versal/
H A Dmain.c76 IMSG("Platform Versal:\tSilicon Revision v%"PRIu8, version); in platform_banner()
84 IMSG("Hardware Root of Trust: Asymmetric[%s], Symmetric[%s]", in platform_banner()
/optee_os/core/drivers/pm/imx/
H A Dpsci.c69 IMSG("psci on ok"); in psci_cpu_on()
78 IMSG("core_id: %" PRIu32, core_id); in psci_cpu_off()
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dmain.c63 IMSG("Platform stm32mp1: flavor %s - DT %s", in platform_banner()
112 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); in plat_console_init()
135 IMSG("DTB disables console"); in init_console_from_dt()
144 IMSG("DTB enables console"); in init_console_from_dt()
406 IMSG("Non-secure SYSRAM [%p %p]", va, va + nsec_size - 1); in configure_sysram()
531 IMSG("WARNING: All debug accesses are allowed"); in init_debug()
759 IMSG("Forced system reset %s", str); in do_reset()
/optee_os/lib/libutils/ext/include/
H A Dtrace.h60 #define IMSG(...) (void)0 macro
62 #define IMSG(...) trace_printf_helper(TRACE_INFO, true, __VA_ARGS__) macro
/optee_os/core/arch/arm/kernel/
H A Dboot.c402 IMSG("Pager pool size: %zukB", in print_pager_pool_size()
508 IMSG("Pager is enabled. Hashes: %zu bytes", hash_size); in init_pager_runtime()
1045 IMSG("OP-TEE version: %s", core_v_str); in boot_init_primary_runtime()
1047 IMSG("WARNING: This OP-TEE configuration might be insecure!"); in boot_init_primary_runtime()
1048 …IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines… in boot_init_primary_runtime()
1050 IMSG("Primary CPU initializing"); in boot_init_primary_runtime()
1066 IMSG("WARNING: This ARM core has NMFI enabled, please apply workaround!"); in boot_init_primary_runtime()
1069 IMSG("WARNING: This ARM core does not have NMFI enabled, no need for workaround"); in boot_init_primary_runtime()
1098 IMSG("Primary CPU switching to normal world boot"); in boot_init_primary_final()
1108 IMSG("Secondary CPU %zu initializing", get_core_pos()); in init_secondary_helper()
[all …]
/optee_os/core/arch/arm/tee/
H A Dentry_fast.c115 IMSG("Reserved shared memory is %sabled", res_shm_en ? "en" : "dis"); in tee_entry_exchange_capabilities()
122 IMSG("Dynamic shared memory is %sabled", dyn_shm_en ? "en" : "dis"); in tee_entry_exchange_capabilities()
126 IMSG("Normal World virtualization support is %sabled", in tee_entry_exchange_capabilities()
135 IMSG("Asynchronous notifications are %sabled", in tee_entry_exchange_capabilities()
/optee_os/core/drivers/firewall/
H A Dstm32_risaf.c258 IMSG("\n\nDUMPING DATA FOR %s\n\n", risaf->pdata.risaf_name); in stm32_risaf_print_erroneous_data()
259 IMSG("====================================================="); in stm32_risaf_print_erroneous_data()
260 IMSG("Status register (IAESR0): %#"PRIx32, in stm32_risaf_print_erroneous_data()
265 IMSG("Status register Dual Port (IAESR1) %#"PRIx32, in stm32_risaf_print_erroneous_data()
268 IMSG("-----------------------------------------------------"); in stm32_risaf_print_erroneous_data()
270 IMSG("Faulty address (IADDR0): %#"PRIxPA, in stm32_risaf_print_erroneous_data()
276 IMSG("Dual port faulty address (IADDR1): %#"PRIxPA, in stm32_risaf_print_erroneous_data()
280 IMSG("Faulty address (IADDR0): %#"PRIx32, in stm32_risaf_print_erroneous_data()
285 IMSG("Dual port faulty address (IADDR1): %#"PRIx32, in stm32_risaf_print_erroneous_data()
289 IMSG("=====================================================\n"); in stm32_risaf_print_erroneous_data()
/optee_os/core/arch/arm/plat-versal2/
H A Dmain.c48 IMSG("OP-TEE OS Running on Platform AMD Versal Gen 2"); in platform_banner()
/optee_os/core/arch/arm/plat-qcom/
H A Dmain.c39 IMSG("Platform Qualcomm: Flavor %s", TO_STR(PLATFORM_FLAVOR)); in platform_banner()
/optee_os/core/drivers/nvmem/
H A Dnvmem_huk.c50 IMSG("nvmem_huk: HUK truncated from %zu to %u bytes", in nvmem_huk_probe()
/optee_os/core/drivers/
H A Dzynqmp_huk.c133 IMSG("CSU authentication disabled, using development HUK"); in tee_otp_get_hw_unique_key()
211 IMSG("HUK ready"); in tee_otp_get_hw_unique_key()
/optee_os/core/drivers/crypto/se050/adaptors/apis/
H A Dsss.c82 IMSG("scp03: current keys"); in se050_rotate_scp03_keys()
89 IMSG("scp03: proposed new keys"); in se050_rotate_scp03_keys()
/optee_os/core/drivers/clk/sam/
H A Dat91_h32mx.c27 IMSG("H32MX clock is too fast"); in clk_sama5d4_h32mx_get_rate()
/optee_os/core/arch/arm/plat-telechips/
H A Dmain.c67 IMSG("There is no HUK in OTP. Starting HUK Provisioning"); in init_huk()

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