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Searched refs:CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/arch/arm/plat-stm32mp2/
H A Dstm32_sysconf.h70 #define CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK GENMASK_32(2, 0) macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c2098 postdiv1 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >> in clk_stm32_pll1_get_rate()
H A Dclk-stm32mp25.c2091 postdiv1 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >> in clk_stm32_pll1_get_rate()