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Searched refs:vmw_write (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_ldu.c115 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, in vmw_ldu_commit_list()
122 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); in vmw_ldu_commit_list()
123 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); in vmw_ldu_commit_list()
124 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); in vmw_ldu_commit_list()
125 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); in vmw_ldu_commit_list()
126 vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay); in vmw_ldu_commit_list()
127 vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay); in vmw_ldu_commit_list()
128 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_ldu_commit_list()
H A Dvmwgfx_fifo.c55 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
130 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | in vmw_fifo_init()
132 vmw_write(dev_priv, SVGA_REG_TRACES, 0); in vmw_fifo_init()
150 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); in vmw_fifo_init()
173 vmw_write(dev_priv, SVGA_REG_SYNC, reason); in vmw_fifo_ping_host()
180 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); in vmw_fifo_release()
186 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, in vmw_fifo_release()
188 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_fifo_release()
190 vmw_write(dev_priv, SVGA_REG_TRACES, in vmw_fifo_release()
H A Dvmwgfx_drv.c697 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_driver_load()
773 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
777 vmw_write(dev_priv, SVGA_REG_DEV_CAP, in vmw_driver_load()
923 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); in vmw_driver_load()
934 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); in vmw_driver_load()
941 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); in vmw_driver_load()
1193 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); in __vmw_svga_enable()
1225 vmw_write(dev_priv, SVGA_REG_ENABLE, in __vmw_svga_disable()
1262 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_svga_disable()
1418 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_pm_restore()
H A Dvmwgfx_irq.c245 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
256 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
351 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); in vmw_irq_uninstall()
H A Dvmwgfx_ioctl.c171 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_fill_compat_cap()
228 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_get_cap_3d_ioctl()
H A Dvmwgfx_kms.c1875 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch); in vmw_kms_write_svga()
1879 vmw_write(vmw_priv, SVGA_REG_WIDTH, width); in vmw_kms_write_svga()
1880 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height); in vmw_kms_write_svga()
1881 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); in vmw_kms_write_svga()
2017 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8); in vmw_du_crtc_gamma_set()
2018 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8); in vmw_du_crtc_gamma_set()
2019 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8); in vmw_du_crtc_gamma_set()
H A Dvmwgfx_cmdbuf.c307 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); in vmw_cmdbuf_header_submit()
311 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); in vmw_cmdbuf_header_submit()
H A Dvmwgfx_drv.h679 static inline void vmw_write(struct vmw_private *dev_priv, in vmw_write() function