Searched refs:pll_enet (Results 1 – 6 of 6) sorted by relevance
145 reg = readl(&ccm_anatop->pll_enet); in decode_pll()301 reg = readl(&ccm_anatop->pll_enet); in mxc_get_pll_enet_derive()744 reg = readl(&ccm_anatop->pll_enet); in enable_pll_enet()748 writel(reg, &ccm_anatop->pll_enet); in enable_pll_enet()751 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) in enable_pll_enet()
285 reg = readl(&anatop->pll_enet); in setup_fec()287 writel(reg, &anatop->pll_enet); in setup_fec()
917 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()935 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()937 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()950 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
176 reg = readl(&anatop->pll_enet); in setup_fec()178 writel(reg, &anatop->pll_enet); in setup_fec()
856 u32 pll_enet; /* 0x0e0 */ member
113 uint32_t pll_enet; /* offset 0x00e0 */ member