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Searched refs:pll8 (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1891 temp |= pll->state.hw_state.pll8; in bxt_ddi_pll_enable()
2010 hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2011 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2172 dpll_hw_state->pll8 = targ_cnt; in bxt_ddi_set_dpll_hw_state()
2277 hw_state->pll8, in bxt_dump_hw_state()
H A Dintel_display.c14005 PIPE_CONF_CHECK_X(dpll_hw_state.pll8); in intel_pipe_config_compare()
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-mdm9615.c78 static struct clk_pll pll8 = { variable
1592 [PLL8] = &pll8.clkr,
H A Dgcc-msm8960.c55 static struct clk_pll pll8 = { variable
3144 [PLL8] = &pll8.clkr,
3372 [PLL8] = &pll8.clkr,
H A Dgcc-msm8660.c27 static struct clk_pll pll8 = { variable
2449 [PLL8] = &pll8.clkr,
H A Dgcc-ipq806x.c82 static struct clk_pll pll8 = { variable
2760 [PLL8] = &pll8.clkr,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun7i-a20.dtsi285 pll8: clk@01c20040 { label
290 clock-output-names = "pll8";