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Searched refs:pll1_ctrl (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dclock.c19 writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), in enable_pll1()
20 &stv0991_cgu_regs->pll1_ctrl); in enable_pll1()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dstv0991_cgu.h35 u32 pll1_ctrl; /* offset 0x64 */ member
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h103 u32 pll1_ctrl; member
/OK3568_Linux_fs/u-boot/board/freescale/vf610twr/
H A Dvf610twr.c299 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()
/OK3568_Linux_fs/u-boot/board/toradex/colibri_vf/
H A Dcolibri_vf.c440 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()
/OK3568_Linux_fs/u-boot/board/phytec/pcm052/
H A Dpcm052.c493 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, in clock_init()