1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _STV0991_CGU_H 9*4882a593Smuzhiyun #define _STV0991_CGU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct stv0991_cgu_regs { 12*4882a593Smuzhiyun u32 cpu_freq; /* offset 0x0 */ 13*4882a593Smuzhiyun u32 icn2_freq; /* offset 0x4 */ 14*4882a593Smuzhiyun u32 dma_freq; /* offset 0x8 */ 15*4882a593Smuzhiyun u32 isp_freq; /* offset 0xc */ 16*4882a593Smuzhiyun u32 h264_freq; /* offset 0x10 */ 17*4882a593Smuzhiyun u32 osif_freq; /* offset 0x14 */ 18*4882a593Smuzhiyun u32 ren_freq; /* offset 0x18 */ 19*4882a593Smuzhiyun u32 tim_freq; /* offset 0x1c */ 20*4882a593Smuzhiyun u32 sai_freq; /* offset 0x20 */ 21*4882a593Smuzhiyun u32 eth_freq; /* offset 0x24 */ 22*4882a593Smuzhiyun u32 i2c_freq; /* offset 0x28 */ 23*4882a593Smuzhiyun u32 spi_freq; /* offset 0x2c */ 24*4882a593Smuzhiyun u32 uart_freq; /* offset 0x30 */ 25*4882a593Smuzhiyun u32 qspi_freq; /* offset 0x34 */ 26*4882a593Smuzhiyun u32 sdio_freq; /* offset 0x38 */ 27*4882a593Smuzhiyun u32 usi_freq; /* offset 0x3c */ 28*4882a593Smuzhiyun u32 can_line_freq; /* offset 0x40 */ 29*4882a593Smuzhiyun u32 debug_freq; /* offset 0x44 */ 30*4882a593Smuzhiyun u32 trace_freq; /* offset 0x48 */ 31*4882a593Smuzhiyun u32 stm_freq; /* offset 0x4c */ 32*4882a593Smuzhiyun u32 eth_ctrl; /* offset 0x50 */ 33*4882a593Smuzhiyun u32 reserved[3]; /* offset 0x54 */ 34*4882a593Smuzhiyun u32 osc_ctrl; /* offset 0x60 */ 35*4882a593Smuzhiyun u32 pll1_ctrl; /* offset 0x64 */ 36*4882a593Smuzhiyun u32 pll1_freq; /* offset 0x68 */ 37*4882a593Smuzhiyun u32 pll1_fract; /* offset 0x6c */ 38*4882a593Smuzhiyun u32 pll1_spread; /* offset 0x70 */ 39*4882a593Smuzhiyun u32 pll1_status; /* offset 0x74 */ 40*4882a593Smuzhiyun u32 pll2_ctrl; /* offset 0x78 */ 41*4882a593Smuzhiyun u32 pll2_freq; /* offset 0x7c */ 42*4882a593Smuzhiyun u32 pll2_fract; /* offset 0x80 */ 43*4882a593Smuzhiyun u32 pll2_spread; /* offset 0x84 */ 44*4882a593Smuzhiyun u32 pll2_status; /* offset 0x88 */ 45*4882a593Smuzhiyun u32 cgu_enable_1; /* offset 0x8c */ 46*4882a593Smuzhiyun u32 cgu_enable_2; /* offset 0x90 */ 47*4882a593Smuzhiyun u32 cgu_isp_pulse; /* offset 0x94 */ 48*4882a593Smuzhiyun u32 cgu_h264_pulse; /* offset 0x98 */ 49*4882a593Smuzhiyun u32 cgu_osif_pulse; /* offset 0x9c */ 50*4882a593Smuzhiyun u32 cgu_ren_pulse; /* offset 0xa0 */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* CGU Timer */ 55*4882a593Smuzhiyun #define CLK_TMR_OSC 0 56*4882a593Smuzhiyun #define CLK_TMR_MCLK 1 57*4882a593Smuzhiyun #define CLK_TMR_PLL1 2 58*4882a593Smuzhiyun #define CLK_TMR_PLL2 3 59*4882a593Smuzhiyun #define MDIV_SHIFT_TMR 3 60*4882a593Smuzhiyun #define DIV_SHIFT_TMR 6 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ 63*4882a593Smuzhiyun | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Clock Enable/Disable */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define TIMER1_CLK_EN (1 << 15) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* CGU Uart config */ 70*4882a593Smuzhiyun #define CLK_UART_MCLK 0 71*4882a593Smuzhiyun #define CLK_UART_PLL1 1 72*4882a593Smuzhiyun #define CLK_UART_PLL2 2 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define MDIV_SHIFT_UART 3 75*4882a593Smuzhiyun #define DIV_SHIFT_UART 6 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define UART_CLK_CFG (4 << DIV_SHIFT_UART \ 78*4882a593Smuzhiyun | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* CGU Ethernet clock config */ 81*4882a593Smuzhiyun #define CLK_ETH_MCLK 0 82*4882a593Smuzhiyun #define CLK_ETH_PLL1 1 83*4882a593Smuzhiyun #define CLK_ETH_PLL2 2 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define MDIV_SHIFT_ETH 3 86*4882a593Smuzhiyun #define DIV_SHIFT_ETH 6 87*4882a593Smuzhiyun #define DIV_ETH_125 9 88*4882a593Smuzhiyun #define DIV_ETH_50 12 89*4882a593Smuzhiyun #define DIV_ETH_P2P 15 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ 92*4882a593Smuzhiyun | 1 << DIV_ETH_125 \ 93*4882a593Smuzhiyun | 0 << DIV_SHIFT_ETH \ 94*4882a593Smuzhiyun | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) 95*4882a593Smuzhiyun /* CGU Ethernet control */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define ETH_CLK_TX_EXT_PHY 0 98*4882a593Smuzhiyun #define ETH_CLK_TX_125M 1 99*4882a593Smuzhiyun #define ETH_CLK_TX_25M 2 100*4882a593Smuzhiyun #define ETH_CLK_TX_2M5 3 101*4882a593Smuzhiyun #define ETH_CLK_TX_DIS 7 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define ETH_CLK_RX_EXT_PHY 0 104*4882a593Smuzhiyun #define ETH_CLK_RX_25M 1 105*4882a593Smuzhiyun #define ETH_CLK_RX_2M5 2 106*4882a593Smuzhiyun #define ETH_CLK_RX_DIS 3 107*4882a593Smuzhiyun #define RX_CLK_SHIFT 3 108*4882a593Smuzhiyun #define ETH_CLK_MASK ~(0x1F) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define ETH_PHY_MODE_GMII 0 111*4882a593Smuzhiyun #define ETH_PHY_MODE_RMII 1 112*4882a593Smuzhiyun #define ETH_PHY_CLK_DIS 1 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ 115*4882a593Smuzhiyun | ETH_CLK_TX_EXT_PHY) 116*4882a593Smuzhiyun /* CGU qspi clock */ 117*4882a593Smuzhiyun #define DIV_HCLK1_SHIFT 9 118*4882a593Smuzhiyun #define DIV_CRYP_SHIFT 6 119*4882a593Smuzhiyun #define MDIV_QSPI_SHIFT 3 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CLK_QSPI_OSC 0 122*4882a593Smuzhiyun #define CLK_QSPI_MCLK 1 123*4882a593Smuzhiyun #define CLK_QSPI_PLL1 2 124*4882a593Smuzhiyun #define CLK_QSPI_PLL2 3 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ 127*4882a593Smuzhiyun | 1 << DIV_CRYP_SHIFT \ 128*4882a593Smuzhiyun | 0 << MDIV_QSPI_SHIFT \ 129*4882a593Smuzhiyun | CLK_QSPI_OSC) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif 132