1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/arch/hardware.h> 10*4882a593Smuzhiyun #include <asm/arch/stv0991_cgu.h> 11*4882a593Smuzhiyun #include<asm/arch/stv0991_periph.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ 14*4882a593Smuzhiyun (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); 15*4882a593Smuzhiyun enable_pll1(void)16*4882a593Smuzhiyunvoid enable_pll1(void) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun /* pll1 already configured for 1000Mhz, just need to enable it */ 19*4882a593Smuzhiyun writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), 20*4882a593Smuzhiyun &stv0991_cgu_regs->pll1_ctrl); 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun clock_setup(int peripheral)23*4882a593Smuzhiyunvoid clock_setup(int peripheral) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun switch (peripheral) { 26*4882a593Smuzhiyun case UART_CLOCK_CFG: 27*4882a593Smuzhiyun writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); 28*4882a593Smuzhiyun break; 29*4882a593Smuzhiyun case ETH_CLOCK_CFG: 30*4882a593Smuzhiyun enable_pll1(); 31*4882a593Smuzhiyun writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Clock selection for ethernet tx_clk & rx_clk*/ 34*4882a593Smuzhiyun writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) 35*4882a593Smuzhiyun | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); 36*4882a593Smuzhiyun break; 37*4882a593Smuzhiyun case QSPI_CLOCK_CFG: 38*4882a593Smuzhiyun writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq); 39*4882a593Smuzhiyun break; 40*4882a593Smuzhiyun default: 41*4882a593Smuzhiyun break; 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun } 44